| Resume alert | Resumes 131 - 140 of 6288 |
C# Bus Driver
Saint Cloud, MN
... ● Currently working on a full emulator with an SDL I/O backend, as well as an FPGA implementation in Verilog on actual Hardware. Custom Language Interpreter (Rust) ● Created a bytecode interpreter for a custom language that can be used either to ... - 2023 Nov 21
... ● Currently working on a full emulator with an SDL I/O backend, as well as an FPGA implementation in Verilog on actual Hardware. Custom Language Interpreter (Rust) ● Created a bytecode interpreter for a custom language that can be used either to ... - 2023 Nov 21
Functional Safety Signal Processing
Toronto, ON, Canada
... Technical Expertise Programming Languages C++, Python, MATLAB, PostgreSQL System Design Tools HFSS, H/PSPICE, Verilog Project Management Tools JIRA, GIT, SVN Requirement Management Tools IBM DOORS Education Doctor of Philosophy(PhD), Electrical and ... - 2023 Nov 20
... Technical Expertise Programming Languages C++, Python, MATLAB, PostgreSQL System Design Tools HFSS, H/PSPICE, Verilog Project Management Tools JIRA, GIT, SVN Requirement Management Tools IBM DOORS Education Doctor of Philosophy(PhD), Electrical and ... - 2023 Nov 20
Firmware/Embedded with Assembler/C/C++
Raleigh, NC
... Wrote test programs and detailed test plans to verify the functional simulations and Verilog outputs to probe the ISA for the behavior of instruction variations (E.G. scalar, vector, component and instruction predication, and branching) to aid in ... - 2023 Nov 18
... Wrote test programs and detailed test plans to verify the functional simulations and Verilog outputs to probe the ISA for the behavior of instruction variations (E.G. scalar, vector, component and instruction predication, and branching) to aid in ... - 2023 Nov 18
Software Engineering Electrical
Fremont, CA
... CD, Ansible Data: ETL, Hadoop, Spark, Tableau Testing: Selenium Blockchain: Ethereum, NFT, Web3, Smart Contract Hardware: Verilog, RTL, Chip Design, Chiplet, EDA, Firmware, CUDA, UVM Leadership: Agile, SCRUM Compliance: PCI, HIPAA CERTIFICATE Azure ... - 2023 Nov 18
... CD, Ansible Data: ETL, Hadoop, Spark, Tableau Testing: Selenium Blockchain: Ethereum, NFT, Web3, Smart Contract Hardware: Verilog, RTL, Chip Design, Chiplet, EDA, Firmware, CUDA, UVM Leadership: Agile, SCRUM Compliance: PCI, HIPAA CERTIFICATE Azure ... - 2023 Nov 18
Verilog, Python, C/C++
Phoenix, AZ, 85003
... Visvesvaraya Technological University Belgaum, India Aug 2017 – Aug 2021 Bachelor of Engineering, Electronics and Communication Engineering GPA 3.8/4 Coursework- VLSI Design, Digital Electronics, Analog Electronics, Verilog and VHDL, Microprocessors ... - 2023 Nov 17
... Visvesvaraya Technological University Belgaum, India Aug 2017 – Aug 2021 Bachelor of Engineering, Electronics and Communication Engineering GPA 3.8/4 Coursework- VLSI Design, Digital Electronics, Analog Electronics, Verilog and VHDL, Microprocessors ... - 2023 Nov 17
C C++ Embedded Systems
Quan 1, 710000, Vietnam
... READING COMPREHENSION C/C++ DESIGN DIGITAL CIRCUIT BASIC VERILOG UNIVERSITY OF INFOMATION TECHNOLOGY - VIET NAM NATIONAL UNIVERSITY HO CHI MINH CITY GPA: 6.54 Subjects Learned: introduction to embedded-system programming, embedded systems, embedded ... - 2023 Nov 16
... READING COMPREHENSION C/C++ DESIGN DIGITAL CIRCUIT BASIC VERILOG UNIVERSITY OF INFOMATION TECHNOLOGY - VIET NAM NATIONAL UNIVERSITY HO CHI MINH CITY GPA: 6.54 Subjects Learned: introduction to embedded-system programming, embedded systems, embedded ... - 2023 Nov 16
Software Engineer Senior Manager
Highlands Ranch, CO
... BSCAD created BS-verification test platform, test vectors, BS-logic in VHDL & Verilog for gate-level simulation. • Maintained code in SABLIME version control system for bug resolution. • Created a web-based form for generating 16-bit ID for the ... - 2023 Nov 15
... BSCAD created BS-verification test platform, test vectors, BS-logic in VHDL & Verilog for gate-level simulation. • Maintained code in SABLIME version control system for bug resolution. • Created a web-based form for generating 16-bit ID for the ... - 2023 Nov 15
Entry Level Fpga Design
New Delhi, Delhi, India
... AREAS OF EXPERTISE Software Proficiency: EDA Tools : ModelSim, Mentor Graphics Tool, OrCAD, Operating System : Windows Family Vlsi Programming Language : Verilog HDL Programming Tool : Xilinx ISE Design Suite 14.5, Designing Tool : ORCAD, Proteus ... - 2023 Nov 08
... AREAS OF EXPERTISE Software Proficiency: EDA Tools : ModelSim, Mentor Graphics Tool, OrCAD, Operating System : Windows Family Vlsi Programming Language : Verilog HDL Programming Tool : Xilinx ISE Design Suite 14.5, Designing Tool : ORCAD, Proteus ... - 2023 Nov 08
Ic Design Engineer
Portland, OR
... feedback technique for 1/f flicker noise up-conversion suppression in SiGe:C BiCMOS process Skills CAD tools: MATLAB, Verilog/VerilogA, Synopsys Hspice, Cadence tools (Spectre, ADE/Virtuoso XL), Cadence EMX, Agilent ADS/Momentum/FEM, Ansys HFSS, ... - 2023 Nov 07
... feedback technique for 1/f flicker noise up-conversion suppression in SiGe:C BiCMOS process Skills CAD tools: MATLAB, Verilog/VerilogA, Synopsys Hspice, Cadence tools (Spectre, ADE/Virtuoso XL), Cadence EMX, Agilent ADS/Momentum/FEM, Ansys HFSS, ... - 2023 Nov 07
C C++ Information Technology
Quan 1, 710000, Vietnam
... EDUCATION University of Information Technology, Vietnam National University, Ho Chi Minh City, Oct 2020 – Present • Major in Computer engineering, GPA 7.54/10, Expect to graduate in July 2024 University Projects MEDIAN FILTER ALGORITHM WITH VERILOG ... - 2023 Nov 03
... EDUCATION University of Information Technology, Vietnam National University, Ho Chi Minh City, Oct 2020 – Present • Major in Computer engineering, GPA 7.54/10, Expect to graduate in July 2024 University Projects MEDIAN FILTER ALGORITHM WITH VERILOG ... - 2023 Nov 03