| Distance: | Resume alert | Resumes 161 - 170 of 5985 |
Embedded Software Firmware Engineer
Placerville, CA
... – Western Digital Firmware/Chip Verification Engineer - Sierra Logic Roseville, CA – (Company closed) 3/2002 to 1/2004 ●Designed and implemented software, firmware, and Verilog code to perform chip verification. I was responsible for the SATA stack ... - 2024 Dec 05
... – Western Digital Firmware/Chip Verification Engineer - Sierra Logic Roseville, CA – (Company closed) 3/2002 to 1/2004 ●Designed and implemented software, firmware, and Verilog code to perform chip verification. I was responsible for the SATA stack ... - 2024 Dec 05
Electrical Engineer Program Coordinator
Maharashtra, India
... IT SKILLS Languages: C, C++, Verilog, VHDL Tools: Operating System: (Unix)Linux,Microsoft Office DATE OF BIRTH: 01-April-1978 Signature : Date : - 2024 Dec 02
... IT SKILLS Languages: C, C++, Verilog, VHDL Tools: Operating System: (Unix)Linux,Microsoft Office DATE OF BIRTH: 01-April-1978 Signature : Date : - 2024 Dec 02
Engineering Intern Design Engineer
Fresno, CA
... SKILLS • Languages: Verilog, SystemVerilog, Python (Programming Language), C++ • FPGA Simulation and Verification Tools: Intel Quartus Prime, Modelsim, Xilinx Vivado • FPGA Board: Xilinx Artix-7, STM32 ARM Cortex-3 • Communication Protocols: JTAG, ... - 2024 Dec 01
... SKILLS • Languages: Verilog, SystemVerilog, Python (Programming Language), C++ • FPGA Simulation and Verification Tools: Intel Quartus Prime, Modelsim, Xilinx Vivado • FPGA Board: Xilinx Artix-7, STM32 ARM Cortex-3 • Communication Protocols: JTAG, ... - 2024 Dec 01
Embedded Linux System
San Diego, CA
... Antenna Management ASIC Contract Position - Analog Devices Inc, Wilmington, MA 7/19 – 12/19 Sr Embedded Engineer Activities: Verilog, C, CLI and GUI, Secure IP Hardware: MAX 10, Analog High-Precision Parts Tools: Intel Quartus Prime, ModelSim, JIRA, ... - 2024 Nov 24
... Antenna Management ASIC Contract Position - Analog Devices Inc, Wilmington, MA 7/19 – 12/19 Sr Embedded Engineer Activities: Verilog, C, CLI and GUI, Secure IP Hardware: MAX 10, Analog High-Precision Parts Tools: Intel Quartus Prime, ModelSim, JIRA, ... - 2024 Nov 24
Electrical Engineer Test
Alexandria, VA
... Synario, Xilinx, PADS, HyperLynx, SPICE, MathCAD, DADiSP, MATLAB, AutoCAD, Altium PCB, KiCAD PCB, FPGA/CPLD: VHDL, Verilog, State-Machine Design, Lattice, Vantis, Altera, Atmel, Xilinx, CUPL, ABEL, Logic Simulation, Layout and timing closure, ... - 2024 Nov 24
... Synario, Xilinx, PADS, HyperLynx, SPICE, MathCAD, DADiSP, MATLAB, AutoCAD, Altium PCB, KiCAD PCB, FPGA/CPLD: VHDL, Verilog, State-Machine Design, Lattice, Vantis, Altera, Atmel, Xilinx, CUPL, ABEL, Logic Simulation, Layout and timing closure, ... - 2024 Nov 24
Postdoctoral Researcher Computer Engineering
San Jose, CA, 95113
... • Hardware Security primitives • FPGA-based design • DACs/ADCs • HDL, Verilog RFIC • LNA • Mixers • Oscillators • VCO • PLL • Power Amplifiers • Synthesizer Software • Cadence Spectre • Cadence Virtuoso • ADS • Altium Designer • Kicad • LTspice P. ... - 2024 Nov 23
... • Hardware Security primitives • FPGA-based design • DACs/ADCs • HDL, Verilog RFIC • LNA • Mixers • Oscillators • VCO • PLL • Power Amplifiers • Synthesizer Software • Cadence Spectre • Cadence Virtuoso • ADS • Altium Designer • Kicad • LTspice P. ... - 2024 Nov 23
Design Engineer Fpga
Ottawa, ON, Canada
... Program Languages: C, Assemble, Verilog, System Verilog, UVM, VHDL, Perl,python, TCL . ASIC Tools: Synopsys, Cadence, Mentor tool sets. FPGA Tools: MODELSIM, SYPLICITY, Xilinx ISE, Xilinx VIVADO, ACTEL Libero IDE, ALDEC. Board Design Tools: PADS, ... - 2024 Nov 16
... Program Languages: C, Assemble, Verilog, System Verilog, UVM, VHDL, Perl,python, TCL . ASIC Tools: Synopsys, Cadence, Mentor tool sets. FPGA Tools: MODELSIM, SYPLICITY, Xilinx ISE, Xilinx VIVADO, ACTEL Libero IDE, ALDEC. Board Design Tools: PADS, ... - 2024 Nov 16
Software Engineer
Morton Grove, IL
... ● Generated a convolutional neural network to classify images and optimized program accuracy using transfer learning on VGG19 model, boosting accuracy by 10% Skills Languages: Python, Java, C, C++, C#, MIPS Assembly, Verilog, JavaScript, SQL, HTML, ... - 2024 Nov 14
... ● Generated a convolutional neural network to classify images and optimized program accuracy using transfer learning on VGG19 model, boosting accuracy by 10% Skills Languages: Python, Java, C, C++, C#, MIPS Assembly, Verilog, JavaScript, SQL, HTML, ... - 2024 Nov 14
Quality Assurance Qa Engineer
Rohnert Park, CA
... 11/1997 –04/1999 TRAINING De Anza College, Cupertino, CA (09/97 – Present), Various OS: Windows 10/8/7/Vista, UNIX/LINUX, Mac OS10/9, Android/iOS, Sun Solaris, Cisco Routers IOS Languages: Python, Shell Script, Perl, Java Script, Java, Verilog, C/C+ ... - 2024 Nov 14
... 11/1997 –04/1999 TRAINING De Anza College, Cupertino, CA (09/97 – Present), Various OS: Windows 10/8/7/Vista, UNIX/LINUX, Mac OS10/9, Android/iOS, Sun Solaris, Cisco Routers IOS Languages: Python, Shell Script, Perl, Java Script, Java, Verilog, C/C+ ... - 2024 Nov 14
C++ C#
Hyderabad, Telangana, India
SUKESH REDDY San Jose 713-***-**** ************@*****.*** PROFILE EXPERIENCE Have above 6+yrs experience in the Automotive, Communications, Healthcare and semiconductor domain using C, C++, C#, Java, Verilog, VHDL, System Verilog, CUDA, Perl, STL, ... - 2024 Nov 13
SUKESH REDDY San Jose 713-***-**** ************@*****.*** PROFILE EXPERIENCE Have above 6+yrs experience in the Automotive, Communications, Healthcare and semiconductor domain using C, C++, C#, Java, Verilog, VHDL, System Verilog, CUDA, Perl, STL, ... - 2024 Nov 13