| Distance: | Resume alert | Resumes 161 - 170 of 5894 |
Electrical Engineer Systems
Bettendorf, IA
Ousmane Lloyd Ntutume ************@*****.*** Phone number: 402-***-**** Address: **** ******* **, *** *, Bettendorf IA, 52722 Objective: Seeking a full-time position as an electrical engineer Skills: •Basic programming (Python, C, java, Verilog, ... - 2025 Mar 08
Ousmane Lloyd Ntutume ************@*****.*** Phone number: 402-***-**** Address: **** ******* **, *** *, Bettendorf IA, 52722 Objective: Seeking a full-time position as an electrical engineer Skills: •Basic programming (Python, C, java, Verilog, ... - 2025 Mar 08
Digital Design Rtl
Portland, OR
... (Jan 2024 – Mar 2026) Relevant Coursework: Microprocessor System Design, System Verilog, Fund of Pre-Silicon Validation, Computer Architecture, Adv Computer Architecture, Assertion Based Verification, Python & Scripting WKSP. Bachelor of Engineering ... - 2025 Mar 06
... (Jan 2024 – Mar 2026) Relevant Coursework: Microprocessor System Design, System Verilog, Fund of Pre-Silicon Validation, Computer Architecture, Adv Computer Architecture, Assertion Based Verification, Python & Scripting WKSP. Bachelor of Engineering ... - 2025 Mar 06
Engineering Intern Electronics
Little Elm, TX
... Design System, CST Studio Suite, Ansys HFSS, Xilinx Vivado, Vitis IDE, LT SPICE, Model Sim Programming languages: Verilog HDL, C,Python Operating System: Linux, Windows WORK EXPERIENCE Hardware Engineering Intern, Quantum Computing Inc., New ... - 2025 Mar 05
... Design System, CST Studio Suite, Ansys HFSS, Xilinx Vivado, Vitis IDE, LT SPICE, Model Sim Programming languages: Verilog HDL, C,Python Operating System: Linux, Windows WORK EXPERIENCE Hardware Engineering Intern, Quantum Computing Inc., New ... - 2025 Mar 05
C++ Full-Stack Web
Sunnyvale, CA
... Proficient in back-end development with C++ and currently learning Verilog and Full-Stack web development. Able to work June 2025 to September 2025. SKILLS Programming Languages: C++ (preferred), Java, Verilog Web Development: Javascript, React, ... - 2025 Mar 05
... Proficient in back-end development with C++ and currently learning Verilog and Full-Stack web development. Able to work June 2025 to September 2025. SKILLS Programming Languages: C++ (preferred), Java, Verilog Web Development: Javascript, React, ... - 2025 Mar 05
Machine Learning C++
New York City, NY
KEVIN WU 929-***-**** ***********@*****.*** www.linkedin.com/in/kevin-wu-7207b2326 LANGUAGE AND IT SKILLS • Languages: Verilog, Matlab, C/C++, Python, SQL • Other Tools: Cadence Virtuoso, JasperGold, LTspice, Pytorch, CAD, Latex, Linux, MS Office ... - 2025 Mar 04
KEVIN WU 929-***-**** ***********@*****.*** www.linkedin.com/in/kevin-wu-7207b2326 LANGUAGE AND IT SKILLS • Languages: Verilog, Matlab, C/C++, Python, SQL • Other Tools: Cadence Virtuoso, JasperGold, LTspice, Pytorch, CAD, Latex, Linux, MS Office ... - 2025 Mar 04
Product Manager Data Center
San Jose, CA
... • Applied NLP-based sequence modeling with LSTM architectures to extract and classify malicious signatures in Verilog and VHDL designs, enhancing the accuracy of pattern recognition and threat classification. • Built a cloud-integrated security ... - 2025 Mar 03
... • Applied NLP-based sequence modeling with LSTM architectures to extract and classify malicious signatures in Verilog and VHDL designs, enhancing the accuracy of pattern recognition and threat classification. • Built a cloud-integrated security ... - 2025 Mar 03
Process Engineer Electrical Engineering
Hillsboro, OR, 97124
... • Designed and executed test scenarios using System Verilog to validate the functionality and timing of the subsystem. Electronics Corporation of India Limited (ECIL) - Hyderabad, INDIA Intern Jan 2021 - May 2021 • Designed an accident detection ... - 2025 Feb 26
... • Designed and executed test scenarios using System Verilog to validate the functionality and timing of the subsystem. Electronics Corporation of India Limited (ECIL) - Hyderabad, INDIA Intern Jan 2021 - May 2021 • Designed an accident detection ... - 2025 Feb 26
Research Assistant Computer Engineering
Fairfax, VA
... work using cloud functions and RESTful APIs RISC-V ISA Processor Aug 2024 – Dec 2024 • Designed a dual-core CPU in System Verilog using RISC-V ISA with pipelines, caches, and cache-coherency • Verified functionality by creating test-benches, unit ... - 2025 Feb 25
... work using cloud functions and RESTful APIs RISC-V ISA Processor Aug 2024 – Dec 2024 • Designed a dual-core CPU in System Verilog using RISC-V ISA with pipelines, caches, and cache-coherency • Verified functionality by creating test-benches, unit ... - 2025 Feb 25
Software Engineer Ios Developer
San Jose, CA
... Wrote chip level & block level test benches using System Verilog and OVM Library. Wrote several OVM Drivers, Monitors, Agents. Wrote several RVM PCIE, SPI, I^2C, BFM’s. Wrote Packet Library for creating Ethernet, IP, UDP, DHCP, ARP packets. Wrote ... - 2025 Feb 25
... Wrote chip level & block level test benches using System Verilog and OVM Library. Wrote several OVM Drivers, Monitors, Agents. Wrote several RVM PCIE, SPI, I^2C, BFM’s. Wrote Packet Library for creating Ethernet, IP, UDP, DHCP, ARP packets. Wrote ... - 2025 Feb 25
Verification Engineer R D
El Jadida, Casablanca-Settat, Morocco
... Core strengths in: • Verification Partitioning and Development Flow • Directed and Coverage Driven Random Verification Flow • I/O Protocols and Controllers Verification TECHNICAL SKILLS Methodologies and UVM,System Verilog (SV), Verilog, System ... - 2025 Feb 24
... Core strengths in: • Verification Partitioning and Development Flow • Directed and Coverage Driven Random Verification Flow • I/O Protocols and Controllers Verification TECHNICAL SKILLS Methodologies and UVM,System Verilog (SV), Verilog, System ... - 2025 Feb 24