Test Engineer Product Development

Dan Grove, San Diego, CA ***** 956-***-**** *********@*****.***

Sr. Test Engineer engaged in hardware, software, firmware design verification and validation activitiesencompassing the entire product development cycle. For US DOD customers, this includes full requirements tracing and successful passage of the stringent acceptance test regimen, gating formal product acceptance. On the commercial side, I'm experienced in high-rely and safety certification testing and tracing to DO-254 and DO-178C standards. I support iterative integration events: publishing objectives, test plans and procedures. Dry-run execution, bug root-cause analysis and hosting/executing run-for-score witnessed testing. I have requirements management experience utilizing both IBM DOORS and JAMA Software tools. I hold an active secret clearance.

FUSE Integration Inc. San Diego 2021 - 2025 (July)

Sr Systems Test Engineer: Executed requirements based acceptance/certification testing on multiple airborne pod mounted systems. Architectures include: Linux CORE(c)-multi-SBC red/black side tactical traffic routing processor; Samsung Galaxy Pad hosted T3 application suite, supporting status/control over the tactical communications radios (CCI). I supported iterative integrations events; publishing test-plans, test-procedures (automated+manual), dry-runs, regression testing, bug reporting/root-cause analysis, end-of-event test reports and requirements-to-test artifacts tracing (under JAMA). I built-out the SIL test-bench env and pushed SW/Firmware updates recorded under configuration management. Pods were delivered to NAWCWD and mounted on F/A-18 and MH60-R platforms, enabling BLOS tactical-edge C2 operations.

DRS Leonardo Aerospace (Daylight Solutions Acquisition), San Diego, CA 2016 – 2020

Sr. Firmware Test Engineer: Test/certification engineer on DIRCM-CIRCM laser-based counter measures (to Heat Seeking Missiles) systems. Phase-1: Developed questaSim systemVerilog test bench to support DO-254 DAL-C functional simulation testing on an embedded micro-controller HDL design operating the Quantum-Cascade-Laser. Published the Test-Plan detailing strategies to demonstrate HDL functional compliance to firmware requirements. Debugged failing tests and logged JIRA bug tickets against the HDL-Design. Published design code-coverage statistics Phase-2: Performed DO-178B DAL-C software driver code-coverage testing (7,000+ lines of code) and analysis, using Vector-CAST. SW Drivers include: MIL-1553, Op-Log, UART/Comm, CRC, SPI/FLASH, and other assorted peripherals. Phase-3: Hardware-In-The-Loop (HITL) testing on the UUT: Constructed a python-based GUI to automate test-script execution on the physical hardware. Automated remote configuration (using VISA) of test equipment: power-supply, function generator, oscilloscope and logic analyzer. Included pop-up prompts to walk operators through trace capture steps on manual hardware tests/diagnostics-routines. The diagnostic suite contained over 60 stand alone tests and exercised design capabilities: built-in-test (IBIT, PBIT, SBIT), remote firmware updates, Zeroize, along with controller operations. Completed project by hosting a run-for-score event attended by DOD acceptance authority (NAWCWD) and military representatives.

Contractor within Parker Aerospace, Irvine, CA (through HCL) 2015 – 2016

Sr. Avionics Hardware Test Engineer: Performed Hardware-In-The-Loop (HITL) validation on the IIM FPGA Firmware portion, of a flight control system, integrated on the Bombardier Global 8000/7000 aircraft. I was responsible for developing TCS scripts that execute on a test-console driving LabVIEW VI based system test-bench env. Test results were captured and managed using NI’s DIAdem software. The flight-control-system is certified to DO-254 DAL-A standards and the In-Circuit validation testing was completed in-advance of Safety-Of-Flight certification for the Bombardier program. The core interfacing

FPGAs(IIM) support the following interfaces: ARINC-429, TTP, RS485(Test-Port), Discrete IOs, LVDTs, and ADC/DACs. The Test Plans, Test Scripts and Test Reports were maintained under MKS. I was directly responsible for developing, executing and maintaining the A429 Bus Fault Test suite used to fully permute fault assertions originated by: FADEC, SFECU and HydSys.

Belcan Tech Services (working within UTC Corp), Phoenix, AZ 2014 - 2015

Sr. Test Engineer: Executed testing and DO-254 DAL-A certification on a Brake Control Unit(BCU) LRU, integration on commercial aircraft. I supported multiple activities including: publishing DO-254 docs, HW test plans, conducting review sessions on docs and test plans; developed and executed HW centric testing on the BCU hardware. I published the EASA Highly-Complex COTS Micro- controller assurance document, outlining the compliance for the Freescale MPC5554 PowerPC microcontrollers embedded within the BCU. I was responsible for writing test procedures for the HVTP document which traces system requirements down to actual HW test-cases and then test execution artifacts.

Advanced Micro Devices (AMD) Austin, TX 2010 - 2013

Sr. Systems Test Engineer (Hardware/Software/Platform Debug/Failure Analysis Team) Member of the System Test team, engaged in platform troubleshooting techniques, methodologies and hands-on experience with test equipment including: high speed LeCroy Oscilloscopes, Logic Analyzers (both Tektronix and Agilent), and hi-speed serial-bus protocol analyzers for SATA, PCI-e, and Hyper-Transport(HT). I was directly responsible for debugging and driving to Root-Cause, various Mobile, Desk-Top, and Server platform related issues reported by internal and external validation teams. System issues include: component level debug, signal integrity problems, software integration issues (BIOS, OS, SW Applications, Diags, ect), and FPGA firmware issues.

Q-Think IC Design Services (now under Qualcomm), San Diego, CA 2007-2009

Supported design verification on the 1st generation, Snap-Dragon SOC, focussed on assertion and coverage-closure on the graphics core. Developed emulation modules, integrated on the RUMI platform

Intel Corp, Chandler, AZ 1996 - 2006

Sr Component Design Engineer: Engaged in multiple aspects of processor, ASIC and SOC development Including: pre-silicon RTL functional simulation, design emulation, post-silicon bring-up and failure analysis.

Education:

University of Vermont School of Engineering Burlington, VT

Computer Engineering 1991

UCSD Ext: Embedded Computer Engineering San Diego, CA

UCSD Ext: LabVIEW Application Developer/Programmer: Received NI Certification LabVIEW AD: 100-***-***** -Experienced with building data acquisition, instrument control and automation test

applications using LabVIEW Virtual Instruments(VI).

Miramar College: Aviation Program, San Diego, CA Instrument, Commercial, Flight Instructor Ground and Avionics Theory curriculum. Teaching Assistant (Spring ’08) -Instructed AVI-196 students with instrument flight operations using the ELITE RC-1 ATD, FAA approved flight simulators.

University of Kansas: Short Aerospace Courses: RTCA DO-254 and DO-178C training, Fall 2018

Instrument Rated Licensed Pilot: Certificate Number 2743243, UCSC Silicon Valley Extension: System and Functional Verification Using UVM 2015, Systemverilog and OOP Testbench Development 2015

Technical Skills:

Software: Unix/Linux/Win CE, C/C++, Assembly: X86, PowerPC, Xscale/ARM, Perl, Python, DXL scripting, Vector-CAST.

Debuggers: AMD’s HDT, Intel’s ITP, JTAG, Xilinx Chip-Scope, MS Windows Debugger, Lauterbach

Designware: VHDL, Verilog, Modelsim/NCsim, SytemVerilog, System-C, Vera, Specman testbench envs, Xilinx ISE, Plan-Ahead, DesignCompiler, Synplicity, and Synopsys Design/FPGA Compilers

Repositories: GitLab, Subversion SVN

Bug Tracking/DBs: JIRA, Taiga, Serena/TeamTrack

Requirements Management SW: IBM DOORS and JAMA

Architectures: PowerPC/MPC5554 Microcontroller, ARM, X86, Nexus, JTAG TCP/IP, IEEE 802.11

Standard Buses: PCI Express, SATA, AMBA, AXI, CAN Bus, ARINC-429/ARINC-818, TTP, RS-232, SM-Bus, I2C, SPI

Lab Test Equipment: Logic Analyzers, Keysight High-Speed Oscilloscopes, DUT config using LabVIEW, bus protocol analyzers.

U.S. Citizen with DOD Secret-Level Security Clearance

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