Ts Sci Mixed Signal

Peter Ateshian

Availability to Start: Immediate if Remote Teleworking

Interview Availability: Monday to Friday 07:00 AM – 05:00 PM PST - 48hr notice min. USA citizen DoD Cleared SAP TS SCI CI-Poly Secret

SUMMARY:

● Peter has 18+ years of experience in digital logic and mixed signal analog design with proficiency in RTL transistor and device circuit design Verilog, VHDL, System Verilog, Design Verification, UVM, OVM, AVM.

● Hands on experience with IP/Block logic design for RISC-V,ARM SPARC MIPS cores ASIC at Rockwell Semiconductor and US Navy.

● He has worked for various renowned organizations, including Honeywell, Intel ICG, AMD NVD & CPU, Oracle/SUN, Cerium Tech, Mahindra, ASML, Northrup Grumman, Raytheon RTX, Boeing, Draper Labs, Amentum, Avantus Federal (SDA), NASA JPL, via Xtrm Designs LLC as CTO and founder.

● Extensive expertise in working with SPARC FPGA, ASIC, ARM, and RISC-V technologies in both FPGA and ASIC SoC CMOS designs.

● Extensive experience in Verilog & VHDL RTL Design for FPGA SPARC RISC-V64 ASIC DSP mixed Signal analog Verilog-A at Sun Microsystems, Apple, Raytheon and US Navy.

● Familiarity with advanced semiconductor processes, including TSMC, IBM 45-22-14nm other 7-3nm finFET process design kit for s-parameters t-parameters Field Solver extraction and conversion from legacy FDSOI designs.

● Hold active DoD TS SCI POLY-CI security clearances and US Navy DoD employee - DARPA PI, US Navy PI.

● Extensive involvement in cutting-edge projects such as AARGM ER-AARGM extended range missile programs, ASML FPGA ASIC design OPC microchip technology.

● Proficient in using Mentor Graphics/ Siemens and other EDA industry-standard tools for verification and Cadence, Synopsys electronic design automation tools. SKILLS:

●

● Neuromorphic processors Intel

power/instruction optimization

● API, HPS, OS, SUN

Microsystems

● 3D FEC, Failure analysis,

Anti-Tamper

● APPLE, Imaging, Oracle,

● Systems Engineering tactical

missile, satellite systems

● ASIC, IMS, Developer,

Systems

● ASP, INTEL, Pascal,

Engineering

● Benchmarking, IP, PEARL,

Phone

● IOS Cisco Network, Software

Development

● Laser Safety and compliance

● BSD, Laser, Camera, UNIX

● C, Ledger, Presentations,

USB3

● C++, Linux, Prime, Validation

● CAD, Logic, Processes,

Verilog

● Cadence, Notes, Processors,

VHDL

● VLSI DESIGN

● X86, Y2K

● Conversion, MBA, RAM

● CPU, Microprocessor, Real

Time

● Database, Windows operating

systems, Robotic Systems

● DSP, Modems, RTOS

● Drivers, MSc, FM

● Electronics, Naval, SGI

● Data extraction and

synchronization

● C++ Python 2.7-3.10 TCL perl

Fortran IV, PL/1

● Verilog VHDL UVM UVMF

proficiency

● Generative AI Graph RAG

EDA UVM applications

● SoC NoC FPGA DSP

hardware design

EDUCATION:

● University of California Berkeley – Berkeley, CA 1979 Master of Engineering in EECS & Business Administration

● University of California Berkeley – Berkeley, CA 1976 Bachelor of Science

● Incomplete PhD Naval Postgraduate School 2020

EXPERIENCE:

Naval Postgraduate School – Monterey, CA Jan 2004 – Present ASIC FPGA Design/Software Engineer

● Calibre nm HDRC HLVS OPC DFM for 23 SoC tapeouts ASIC CMOS TSMC RF 45/22/14/10/7 nm

● 3nm process design kit PDK development s-parameters t-parameters Field Solver models Eldo Spectre Mentor Graphics EDA

● Mixed signal design RSNS folded A/D

● Calibre advanced Work- with Intel Litho Group on PSM corrections on gates - Training and benchmarking OPC/RET test-cases.

● Completed AMD Integrated Circuits assessment of <100-75nm technology shrinks on K9 microprocessor devices with Calibre Litho/PSM.

● Completed AMD Flash NVD Device 369 Calibre HLVS/HDRC Tape out resulting in AMD-MGC/MCD First Pass Production silicon Success Story.

● Completed AMD Y2K corrections of Calibre/IC rules for entire NVD rules suite for CS19 to CS59 due to OPPOSITE command EDA software code change.

● Flare angled ESD devices and diagonal gate devices are now all correctly checked rather than being deleted.

● Completed SUN Microsystems Gemini block conversions using Calibre HLVS and Simplex flows for RC extraction.

● Identified flow issues with feedthroughs and lost nets/Ports.

● Developed Lsim circuit simulation verification for FP Multiplier Mega-cells with Dynamic FF with static keepers and stacked gate logic for clock/power disable and full scan.

● Converted Bipolar RF design to newer BiCMOS technology and verified design with Calibre HLVS

● IP reuse required Converted ARM9 Core to be verified, benchmarked and cataloged for next generation process.

● Installed and deployed Calibre as Key Verification tool in Conexant IP re- use programs using ARM7, ARM9 core and benchmarking as three way example.

● Calibre successes at Silicon Access Networks, LSI Logic and Siliconix.

● Design and EDA Clients included TRW Avionics, AMD-NVD, Sony, Fujitsu, ARM, TeraSystems and Silicon Perspectives/Cadence

XTRM Designs LLC Jul 1992 – Present

Consultant

● CTO / Founder /Principal/Software Engineer Developer/Design AI-ML Technology NAML NWIC San Diego NAVAL APPLICATIONS for MACHINE LEARNING since 2017-2023

● Engineering & Technical Consulting/Services Company supporting IC design, implementations and use of tape-out verification EDA tools for clients.

● Implemented AMD Y2K Calibre/IC rule corrections for CS19 to CS59 Tape Outs due to the opposite command EDA software code change.

● Completed SUN Microsystems Gemini block conversions using Calibre HLVS and Simplex flows for RC

● extraction.

● Delivered an advanced production solution to extricate flat GDS2 layers from a silicon ensemble, rebuilding with CheckMate when the Cheetah database was too large to allow hierarchical output.

● Assisted design groups in deploying Calibre to replace CheckMate/Hercules/Dracula in 13 processes ranging from EEPLD/Flash to RF-Bipolar, exceeding schedule by completing the project in only 11 months. Honeywell Jan 2023 – Apr 2023

Sr. Electronic Design Engineer

● PCB simulation temperature frequency-voltage feedback design. US Navy Naval Postgraduate School

Sept 2006 – Jan 2024

Sr. Software & Firmware Engineer

Sr. ASIC FPGA Design Engineer

● Undersea Lidar imaging and laser communications.

● FSO laser mimo communications with machine learning compensation.

● Raspberry Pi3 Debian Ubuntu Rasbian Python SciPy NumPy QR code optical MIMO communications signaling Open CV C++ ARM IoT eBook US Navy EC3800 course PSoC-ARM Design

● 'Xtrm' Designs LLC, was initially funded by Mentor Graphics, TeraSystems, Conexant, US Navy and SUN Microsystems.

● Five startups with IPO and M & A exits.

● IoT REST API MEMS sensors C++ and ARM assembly drivers, developed embedded device connect ARM network and Sensor Tile, ST Microelectronics, IBM Watson Bluemix node red, Heroku Salesforce, zebra's zatar network, postman Cloud connectivity.

● QR code barcode reader video camera app text conversion then Wi-Fi or wired transmission to cloud for analytics.

● IoT details: C++ www.mbed.org see GR Peach video QR code reader using ARM Cortex A-9 Series, RTOS embedded-OS listed under Xtrm Designs LLC; Python and Raspberry Pi 3 quad ARM Cortex A-53 Series/Raspbian OS NPS CS Department course CS2020.

● C++ Sensor Tile ST Microelectronics two Processor Cortex M0 and m4; Intel Arduino 101 C++ D2000 Curie SoC with Arc, ARM Cortex M0 and Atom/x86 tri Processor and integrated MEMS sensors.

● TRNG and next generation Iridium modem Femto Satellite. MindSpeed Technologies Jan 2014 – Jan 2015

Navy/NPS Manager Specialist

● Femto Satellite swarm network Design internet of space (IoS).

● Laser submarine optical detection system patent application.

● ARM Cortex A 9 IoT c++ QR code demonstration.

● Multiple IP (ARM7, ARM9/ 11 Cortex, SPARC, DSP, Analog mixed signal IP cores) integration, benchmarking and SoC designs NPS Femto Satellite redesign Undersea LiDAR research and development Synthesis and Scan design regression, TRW, SUN, Mentor Graphics, C, C++, OOP 200-400M Device Tape-out and silicon failure analysis (FIB).

● Mentor Graphics, AMD Memories, NVD CPLD Div., Intel ICG, Sun Microsystems, Conexant Systems, MindSpeed Technologies, Jazz Semiconductor, ARM, Ikanos Communications, LSI LOGIC.

● CMOS RSNS A/D converter design for low power micro morphing air-land UAV and Autonomous Robotic Systems.

● Detailed experience with real-time embedded, C, C++, UNIX, Linux, Minix and modified Windows operating systems.

● Silicon-polycrystalline Diamond new device technology advances (Sp3) for GaN & InP HEMTs.

● Developed specialists for independent contracting in Integrated Circuit HLVS, OPC-HDRC, and RET.

● Synthesis analysis, formal verification, debug and redesign.

● Switched Capacitor Circuits and Filters, Matched Z transform, Clock/Power Noise Alias reduction techniques Switched Capacitor Filter.

● ARM 7-9 Micro Controller Hard silicon- cores IP synthesis validation, benchmarking, and Verification for SoC applications.

● Low Power CMOS Circuit synthesis techniques for medical devices, CSEM Zero Power Libraries for watch and minimum power application - Zero Power input transition Detection circuits.

● Xilinx Vivado and Intel Altera neural networks Applications for radar pattern signature recognition. Xtrm Designs llc

Jan 1992 – Jan 2004

Technical Engineer – Communications Telecom

● Provided the leadership and technical direction for VLSI Full custom & ASIC design and complex EDA/CAD flows, including new RISC-V CHISEL Scala technology implementation applications for IC design.

● FPGA prototyping of RISC-V Yocto Linux, ARM7, ARM9 CortexM0/1 - CortexA8/9 based SoCs and multi-processor devices.

● TrustZone subsystems (TEE) ARMv7 32 & ARMv8a 64-bit.

● Xilinx with Embedded Design Kit (EDK) Toolset: Xilinx Platform Studio (XPS).

● Systems-On-Chip (SoCs) Processors (PowerPC, MicroBlaze, Vivado, Zynq 7000-ARM) Virtex XC2-5.

● Intel's Altera Quartus II, Pro Prime Arria 10 HPS (embedded dual ARM Cortex A9) FPGA VHDL and Verilog Applications.

● FPGA Chip Scope verification and debug.

● Recently worked on NDA limited details for USB3, PCIe Gen3/Gen4, for Game systems, DDR3-DDR4-DDRx, Low Power DDRx, 4K+ HDMI, UHD, MIPI, Gigabit Ethernet.

● QSound psycho-acoustic 3D sound DSP and ASP algorithms in Silicon CMOS implementation.

● Kali RHE Ubuntu Debian Linux and BSD Unix kernel open source Raspbian drivers.

● FPGA architecture and tools Experience in Brief: eBook on FPGA ARM Cortex and mixed signal Applications.

● Years of C/C++ code/programming experience Unix Linux C/C++since

● Digital Signal Processing such as filters, FFT, and wireless concepts Cyclotomic DSP filters, Intel 2910/20 since 1980 DSP pSoC FPGA 27yrs HLS, OpenCL, SystemC Since 2010.

● Exemplar Logic FPGA EDA tool box for synthesis simulation of Verilog VHDL variants.

● Mentor Graphics Corp, Conexant MindSpeed, AMD NVD.

● Finite state machine, FSM design, TMR space Applications TMR design.

● ASIC chip CPU Data path synthesis design and timing optimization.

● Oracle SPARC Intel icg missiles x86 embedded dram.

● Military confidential DSP analog mixed signal Applications.

● Actel Micro Semi fusion Mixed signal FPGA DSP ARM core Applications for US Navy(2007-2012) ICT Inc Jul 1994 – Mar 1996

Vice President Engineering

● Product redeployment of 22 of 27 EEPLD products with corrected design and production flaws over an 18-month period.

● Introduction of a Zero Power Complex EEPLD to compete in the 5-7ns arena.

● Tools were Virtuoso/Composer/Dracula and Mentor CAECO.

● Cool RISC microprocessor from CSEM Switzerland as a new Zero power technology for ICT.

● EM Marin SA Switzerland was approached to purchase ICT.

● ICT Lost funding as a restart in 1996.

Parsec Software Dec 1993 – Jul 1994

Vice President

● Pearl - Mixed Mode/Hierarchical STATIC Timing Analyzer.

● During the 8-month period I completed sales with Texas Instruments, Fujitsu, Hitachi, Mentor (design group), AT&T, and IDT/QED.

● Company was sold to Cadence.

Exemplar Logic, Apple, Silicon Graphics, CISCO/StrataCom, Hitachi Jul 1992 – Jul 1994 Multi-Source Integration MSI

President

● Support/Business Development/Sales Consulting & Services Company which morphed into Xtrm Designs LLC, XDllc, Consulted on SUN microprocessor Tsupernami/Spitfire/Cheetah/Gemini and Three AMD Flash devices, QSound analog SCF 3D Sound devices and Hearing Aid/Cell Phone MEMS microphones.

● Submitted DARPA SBIR for MEMS Microphone Study using Draper Labs device.

● TRW-Consulted in the redesign of several Obsolete Military Devices into current FPGA technology. Mentor Graphics/Silicon Design Labs Silicon Computer Systems Mar 1985 – May 1991 Technical Account Manager

● Technical Engineering Support/Business Development/Sales Consulting & Services Company Strategic Technical Account Manager: - SUN & APPLE - completed $2.8M in first year.

● Over Quota six years in a row, Silicon Valley territory $2.0M Engineer/Apps Manager: - Over Quota six years in a row.

● Design Manager San Jose for SDL - Apple Graphics Display chip. Atari Home Computer VLSI Jan 1983 – Jan 1985

Design Engineer

● Cost reduction and power conservation with CMOS conversions for DRAM Controllers and PLD devices.

● Eliminated LC timing delay lines that were unreliable in production due to humidity construction factors.

● Implemented polynomial counter circuits for video and timing functions for AT520 next generation computer.

● Design robotic circuits and controllers for independent operations and master controller. EG&G Reticon Jan 1981 – Jan 1983

Analog Design Engineer

● Switched Capacitor Filters for 2400 - 19.2Kbd analog modems, SCF programmable array device, EDA tool development for the conversion of continuous time pole/zeros to Matched Z transform Filter poles/zeroes into Capacitor shapes/Arrays in GDSI and GDSII polygons. Jan 1979 – Jan 1981

Plantronics Electronic Design Engineer

● DSP for Cyclotomic Digital Filters using one bit A/D and 2900 Bit-slice AMD microprocessor and Switched Capacitor Filter analog implementation of 30 channel multiplexed DTMF filters.

Contact this candidate