| Resume alert | Resumes 141 - 150 of 6290 |
Ic Design Engineer
Portland, OR
... feedback technique for 1/f flicker noise up-conversion suppression in SiGe:C BiCMOS process Skills CAD tools: MATLAB, Verilog/VerilogA, Synopsys Hspice, Cadence tools (Spectre, ADE/Virtuoso XL), Cadence EMX, Agilent ADS/Momentum/FEM, Ansys HFSS, ... - 2023 Nov 07
... feedback technique for 1/f flicker noise up-conversion suppression in SiGe:C BiCMOS process Skills CAD tools: MATLAB, Verilog/VerilogA, Synopsys Hspice, Cadence tools (Spectre, ADE/Virtuoso XL), Cadence EMX, Agilent ADS/Momentum/FEM, Ansys HFSS, ... - 2023 Nov 07
C C++ Information Technology
Quan 1, 710000, Vietnam
... EDUCATION University of Information Technology, Vietnam National University, Ho Chi Minh City, Oct 2020 – Present • Major in Computer engineering, GPA 7.54/10, Expect to graduate in July 2024 University Projects MEDIAN FILTER ALGORITHM WITH VERILOG ... - 2023 Nov 03
... EDUCATION University of Information Technology, Vietnam National University, Ho Chi Minh City, Oct 2020 – Present • Major in Computer engineering, GPA 7.54/10, Expect to graduate in July 2024 University Projects MEDIAN FILTER ALGORITHM WITH VERILOG ... - 2023 Nov 03
Sql Server Software Development
Plano, TX
... Programming Languages: T-SQL,Oracle SQL, PL/SQL, PostgreSQL, Kafka, MongoDB, java, C++, C#, VHDL, Verilog, FPGA Cloud Technologies: AWS, Microsoft Azure, Snowflake. Ticketing Applications: JIRA, Service now. Microsoft Office: MS Word, MS Excel, MS ... - 2023 Nov 01
... Programming Languages: T-SQL,Oracle SQL, PL/SQL, PostgreSQL, Kafka, MongoDB, java, C++, C#, VHDL, Verilog, FPGA Cloud Technologies: AWS, Microsoft Azure, Snowflake. Ticketing Applications: JIRA, Service now. Microsoft Office: MS Word, MS Excel, MS ... - 2023 Nov 01
Design Engineer Rtl
San Jose, CA, 95118
... channeled low-power DMA for controllers Verified DDR3 interface using System Verilog (VMM), Designed DSP blocks (FIR/IIR, FFT) Designed High Speed Serial Link (6 GHz) using 65nM technology (IBM) Designed CACHE controller (MESI and MOESI) for MPU. ... - 2023 Oct 31
... channeled low-power DMA for controllers Verified DDR3 interface using System Verilog (VMM), Designed DSP blocks (FIR/IIR, FFT) Designed High Speed Serial Link (6 GHz) using 65nM technology (IBM) Designed CACHE controller (MESI and MOESI) for MPU. ... - 2023 Oct 31
Design Engineer Electrical
Greensboro, NC
... (Nov/2022-PRESENT) Skills Altium Designer MATLAB OrCAD AutoCAD Allegro Six Sigma Black Belt Proteus Six Sigma Green Belt PIC C compiler Six Sigma Yellow Belt C++ C Programming for Embedded Applications Python LabVIEW C# IPC-A-610 FPGA VHDL, Verilog ... - 2023 Oct 31
... (Nov/2022-PRESENT) Skills Altium Designer MATLAB OrCAD AutoCAD Allegro Six Sigma Black Belt Proteus Six Sigma Green Belt PIC C compiler Six Sigma Yellow Belt C++ C Programming for Embedded Applications Python LabVIEW C# IPC-A-610 FPGA VHDL, Verilog ... - 2023 Oct 31
IT technician
Lubbock, TX
... Programming Languages: Python, HTML, Java, C, Verilog, Assemble language. General Programs: Microsoft Office (Word, Excel, PowerPoint) Languages: English, French, basic Spanish. Skills: OOP, Data structures, Algorithms,Operating systems, Computer ... - 2023 Oct 28
... Programming Languages: Python, HTML, Java, C, Verilog, Assemble language. General Programs: Microsoft Office (Word, Excel, PowerPoint) Languages: English, French, basic Spanish. Skills: OOP, Data structures, Algorithms,Operating systems, Computer ... - 2023 Oct 28
Soc Design Hardware Engineer
Pakistan
... CGPA: 3.00/4.00 2018 Final Year Project (Bachelors) “Development of MIL-STD-1553 Data Bus Transceiver on FPGA” Developed MIL-STD-1553 to learn practical hardware modeling using Verilog and verified it behavior using FPGAs. SKILLS • Verilog/ System ... - 2023 Oct 28
... CGPA: 3.00/4.00 2018 Final Year Project (Bachelors) “Development of MIL-STD-1553 Data Bus Transceiver on FPGA” Developed MIL-STD-1553 to learn practical hardware modeling using Verilog and verified it behavior using FPGAs. SKILLS • Verilog/ System ... - 2023 Oct 28
Layout Designer Design
San Jose, CA
... team · Expertise in Modeling of an extremely sensitive superconducting nanowire single photon detectors (SNSPD) · Expertise in Verilog programming modeling from Cadence · Expertise in Deep space link · Expertise in optic detectors for deep space ... - 2023 Oct 23
... team · Expertise in Modeling of an extremely sensitive superconducting nanowire single photon detectors (SNSPD) · Expertise in Verilog programming modeling from Cadence · Expertise in Deep space link · Expertise in optic detectors for deep space ... - 2023 Oct 23
Digital Design Test Engineer
La Jolla, CA
... SKILLS Languages: System Verilog, Python, C, C++, Java, VBA Software: Matlab, Hspice, Virtuoso, PSpice, KiCAD, Spotfire, Quartus Prime WORK EXPERIENCE Qualcomm Technologies Inc May-2022-Present San Diego Product and Test Engineer • Headed the ... - 2023 Oct 22
... SKILLS Languages: System Verilog, Python, C, C++, Java, VBA Software: Matlab, Hspice, Virtuoso, PSpice, KiCAD, Spotfire, Quartus Prime WORK EXPERIENCE Qualcomm Technologies Inc May-2022-Present San Diego Product and Test Engineer • Headed the ... - 2023 Oct 22
Development Engineering Software
Omaha, NE
... Programming Skills C#,Java,C++,VB,Assembly,MATLAB,Object oriented,C, JavaScript, JQuery,CSS,HTML,HTML5, XML, ASP.net, Web Services, .NET REMOTING, SQL, MYSQL, ORACLE, WPF, Multithreading programming,Android, Socket Programming,, VERILOG, image ... - 2023 Oct 19
... Programming Skills C#,Java,C++,VB,Assembly,MATLAB,Object oriented,C, JavaScript, JQuery,CSS,HTML,HTML5, XML, ASP.net, Web Services, .NET REMOTING, SQL, MYSQL, ORACLE, WPF, Multithreading programming,Android, Socket Programming,, VERILOG, image ... - 2023 Oct 19