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Design Engineer Circuit

Location:
San Jose, CA
Posted:
July 06, 2025

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Resume:

S. Reza Bahadur – (US born Citizen)

Fremont, CA

510-***-**** *********@*******.***

OBJECTIVE:

Seeking a Analog IC Design Engineer position. 13 years of design experience. SKILLS:

Proven track record of passing silicon. Complete end-to-end circuit design lifecycle experience : product definition, chip architecture, block architecture, block circuit design, layout, IBIS model development, chip level cosim, QnR simulations (Totem, EMIR, EOS), tapeout, wafer sort, IC characterization, IC release. Team player, Hands on lab experience, Great communication. Supervised : 5 analog design engineers, 4 layout engineers, 3 cosim engineers, 4 characterization engineers, 4 wafer sort test engineers.

Unique strengths beyond circuit design : driving/executing layout, driving COSIM & DV verification, driving wafer sort, & driving characterization/bring-up of chip/subsystem. WORK EXPERIENCE:

2015- Present : Intel Corporation – Staff IC Design Engineer - ( Silicon Photonics team)

• Design : Photonics EIC - PMIC – High Power Current DAC : 13 bit current DACs, 10 bit current DACs - high power. – Analog Technical Lead

[ 40 nm TSMC process ]

[ 22 nm Intel process ]

[ 14 nm Intel process ]

Designed 200mA current DACs to drive laser diodes in photonic IC ( PIC ). Low headroom <0.3V

& DNL < 0.2 LSB, INL < 0.5 LSB – over PVT and Code. Entire design cycle: Architected chip size from scratch. Architected circuit architecture, bump assignment and allocation, floorplanning, Chip top owner. DACs used to bias : LD, SOA, VOA, and Ring Heaters.

• Design : TIA chip : TIA front end, AGC, Driver for 112 GBPS and 224 GBPS PAM4 Optical Channel Interface

[ 90 nm BICMOS GF 9HP process ]

Worked on TIA Design for 112Gbps & 224Gbps PAM4 data. Input PD current 100uA-pp-2.5mA- pp (Optical power -10dBm to 4dBm), Peak-to-Peak Output of 400mV, Gain ranges from 44dB- 72dB.

Designed AGC. Sub-circuits included a Peak-Detector, 6-bit Binary IDAC to set Peak-to-Peak output for TIA, and a 7-bit RDAC to emulate TIA in Digital-calibration mode. Designed output open drain driver to achieve -15dB return loss at Nyquist, for each data rate. Silicon correlated very tightly with simulation/modeling. Completed successful tape out of multiple variants of TIA, and multiple data rates.

• Design : PAM4 MZM Driver - SERDES Stand-Alone TX IC. 64 GBPS: CTLE, Transmission Line Driver, MZM Driver.

[ 40 nm TSMC process ]

Designed complete standalone IC TX Driver, to drive Mach-Zender Modulator to Modulate Laser light source for High Speed Optical Communications System. Full in-depth understanding and study of architecture, system, and interaction between Silicon IC and Photonics IC.

• Design: Common Lane for TIA chip : RC oscillator, VBG, VTOI, AMUX, ESD scheme, VLDOs, POR blocks.

[ 90 nm BICMOS GF 9HP process ]

Designed all the DC fundamental blocks for the common lane of the chip.

• Design : 6 bit ADC design – 1 GBPS: 3 Stage Pipeline ADC

[ 45 nm TSMC process ]

Designed ADC with 3 pipeline stages. Each stage generated 3 ADC bits, which provided 1 extra bit for error correction. DAC (to generate quantized 3-bit ADC signal), Summation (to generate error residue), and Amplification (to generate full scale residue from error residue) 2012- 2015 : Altera Corporation – Senior IC Design Engineer - (High Speed SERDES IO team)

• Design : SERDES RX AFE (Analog Front End) - 4-28 Gbps CTLE with TIA based drain degeneration. 10-28 Gbps VGA. 4-10 Gbps QPI (pmos based CTLE)

[ 20 nm TSMC process ]

Designed a CTLE to operate at 19 GHz with 16 dB ac peaking and -6 dB to 8 dB DC gain, with 2 common mode feedback loops to main CTLE stage and TIA stage, with body bias offset calibration.

• Design : RX CTLE, Voltage Bandgap, Voltage Regulator, Analog Test bus, AUX Mux

[ 14 nm Intel process ]

Designed 2 stage CTLE with TIA second stage. Designed a 0.7V reference voltage, using 1.8V supply, with <1% variation across PVT and monte carlo simulation.

• Design : Voltage Bandgap, Voltage Regulator

[ 28 nm TSMC process ]

Designed a 0.7V reference voltage, using 1.8V supply, with <1% variation across PVT and monte carlo simulation.

2009-2011 : UC Davis, Graduate Student Researcher – High Power Frequency Multipliers Design and fabricate a high power frequency doubler, at 3.33 GHz, using a GaN power amplifier and tuned matching networks.

2008 - 2009 : Intersil, Milpitas CA - Application Engineer As lead Application Engineer - Developed application notes, user guides, and GUI design for all Light Sensor and Proximity Sensor product lines for Apple Iphone and Google Pixel phones. EDUCATION:

University of California, Berkeley, CA. B.S. – Electrical Engineering and Computer Science – 2009 University of California, Davis, CA. M.S. – Electrical and Computer Engineering - 2012 PATENTS:

• “Mach-Zehnder Modulator Driver” 2019. Syed Islam, Raghuram Narayan, Reza Bahadur. MZM Driver for PAM-4 application.

• “Design of Embedded Wafer Level BGA (EWLB) Packaging for GBPS Applications” 2017. Reza Bahadur, Vivek Raghuraman.

• “Harden Sense Amplifier Offset Cancelation Scheme with Memory Mapped Interface Block” 2013. Reza Bahadur, Allen Chan.

• “Spatial Bus Routing for Modular Gate Circuit Blocks” 2013. Reza Bahadur, Thomas White. PUBLICATIONS:

"4 Tb/s Optical Compute Interconnect Chiplet for XPU-to-XPU Connectivity“ in 2024 IEEE Hot Chips Symposium. Reza Bahadur – Silicon Photonics Products Division Intel.

"High Power, Wideband Frequency Doubler Design using AlGaN/GaN HEMTs and Filtering" in 2011 European Microwave Symposium September 26, 2011. Reza Bahadur, G.R. Branner.

“Perform Coarse And Fine Correction With Less Costly Dual DCPS” in Electronic Design October 2, 2008. Reza Bahadur, Tamara Schmitz, Mike Wong.

EQUIPMENT EXPERIENCE:

Equipment: DCA (Digital Communications Analyzer), VNA/PNA (Network Analyzer), Spectrum Analyzer, Frequency Synthesizer, Sweep Oscillators, Function generator, Multimeter, Power supplies. Languages: IBIS models, Verilog-A, HSpice, Python, Ocean scripting, TCL scripting, MATLAB, C, C++ Software: Cadence Virtuoso (ADE XL, Maestro, Layout XL), Ansys Totem, Ansys Helic, Matlab, Hspice, Cadence Allegro, JMP, Logisim, Avanwaves, Cosim Waveform Viewer



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