|
Resume alert |
Resumes 11 - 20 of 455 |
Santa Clara, CA, 95050
... Excellent Verilog/SystemVerilog, VHDL RTL coding skill Extensive working knowledge of digital logic, analog circuit and mixed-signal design Proficiency in C, Matlab/Simulink and Python programming Working knowledge of Vitis HLS Experience with AXI4 ...
- Feb 06
Los Gatos, CA
... 2002 – 2008 Verification Architect Nvidia Santa Clara CA Led 17 software engineers developing C model and Verilog RTL verification infrastructure of 50+ million gate graphics integrated circuits. Supported teams at multiple sites in U.S. and India. ...
- Jan 19
San Jose, CA
... C, MATLAB, python, SIMULINK, Verilog, Xilinx, Python, Perl WORK EXPERIENCE Aug’18 – Mar ‘23 Technical Program Manager (50% time) at Intel Research Lab, Wireless Multi-Communication Research Lab (WMCR), Santa Clara, CA, USA. MuMIMO with GNN: Working ...
- Jan 16
San Jose, CA
... SKILLS _ Languages: Java, Python, MATLAB, C, C++, LaTeX, Verilog, Chisel, JavaScript, TypeScript, Swift, HTML, CSS, Assembly Frameworks: Spring Boot, Flask, Streamlit, Node, Express, React, Angular, Bootstrap, Hadoop MapReduce Tools: Numpy, Pandas, ...
- Jan 12
San Jose, CA, 95126
... ORGANISATION: MAVEN SILICON, BANGLORE August 2022 – September 2022 Objective was to design the basic digital circuits using Verilog, the tools used were Intel Quartus Prime and ModelSim. Obtaining RTL schematic and waveforms of various circuits and ...
- Jan 10
San Jose, CA
... commissioning and troubleshooting Instrumentation P&ID reading Driver license Hobby Programming on C and Verilog language various microcontrollers. Develop various electronic board and integrate with IOT. Construct CNC machine. Deploy LORAWAN net.
- 2023 Dec 11
Fremont, CA
... CD, Ansible Data: ETL, Hadoop, Spark, Tableau Testing: Selenium Blockchain: Ethereum, NFT, Web3, Smart Contract Hardware: Verilog, RTL, Chip Design, Chiplet, EDA, Firmware, CUDA, UVM Leadership: Agile, SCRUM Compliance: PCI, HIPAA CERTIFICATE Azure ...
- 2023 Nov 18
San Jose, CA, 95118
... channeled low-power DMA for controllers Verified DDR3 interface using System Verilog (VMM), Designed DSP blocks (FIR/IIR, FFT) Designed High Speed Serial Link (6 GHz) using 65nM technology (IBM) Designed CACHE controller (MESI and MOESI) for MPU. ...
- 2023 Oct 31
San Jose, CA
... team · Expertise in Modeling of an extremely sensitive superconducting nanowire single photon detectors (SNSPD) · Expertise in Verilog programming modeling from Cadence · Expertise in Deep space link · Expertise in optic detectors for deep space ...
- 2023 Oct 23
San Mateo, CA
... Good IP knowledge in some PHY blocks PCIe Familiar with VHDL, Verilog, familiar with VHDL, Verilog, C and C++, System Verilog, and assembly language and a python script. Sound knowledge in test cases, SOC simulation, and UVM methodology. Solid ...
- 2023 Sep 21