Design Engineer Rtl

Alex Kumets

**** ***** **. *** ****, CA *****

408-***-**** *******@*****.***

ASIC/SOC VERIFICATION/DESIGN ENGINEER

HIGHLIGHTS

Have thorough understanding of different RTL design and verification strategies suited for today's applications.

Architected Low Power verification for multi-power domains SOC. Have extensive experience in planning, implementation and execution of the ASIC projects.

Developed test plans and UVM based verification environment from scratch. Developed SystemVerilog models for Mixed Signal validation. RTL Design and Design Verification with extensive start to finish project experience. Hands on experience on block level, gate level, and chip level verification. EXPERIENCE

Defined verification methodology using UVM/SystemVerilog for the multisite teams Developed Block, Sub System and Full chip Verification Environment and Testbenches using SystemVerilog and Universal Verification Methodology (UVM) Designed agents in UVM/SystemVerilog environment for Low Power verification combining UPF and UVM. Used PowerArtist for power estimations (RTL and GLV) Verification based on architectural/micro-architectural specification review and analysis. Implemented testbench and verification components using UVM/SystemVerilog Developed and Validated Low Power Constraints (UPF/IEEE1801) for multiple voltage and power domains

Performed Power Aware GLS validation for the peak/average dynamic and total power Developed UVM based verification (PCIe – NVMe) for SSD controller (Dynamic Wear Leveling, AES crypto block, DMA)

Developed RTL for the Phy layer PCIe3.1 (PMA serdes): clock and data recovery Verified Low Power Design using MVSIM, MVRC (SNPS), and Conformal LP (CDNS), wrote UPF scripts for the low power verification and synthesis. Transferred RTL from ASIC to FPGA for emulation.

Verified data link layer for PCI-E. Used VIPs from Cadence, Synopsys Resolved LP related Multi-mode, Multi-corner MMMC, STA timing corners and PVT issues. Transformed verification components from OVM/SystemVerilog and VMM to UVM Developed UVM infrastructure for block and partition level verification Wrote scripts for register layer modeling in the Cadence environment Performed static timing analysis (STA) using PrimeTime Designed power controllers for low-power design. Used Spyglass for linting Performed logic synthesis using Synopsys tools (design and power compilers) Wrote scripts for low power design using UPF

Designed verification system for RapidIO using RVM (Vera) and SystemVerilog Wrote SystemVerilog assertions (SVA) for functional coverage Verified multi-channeled low-power DMA for controllers Verified DDR3 interface using System Verilog (VMM), Designed DSP blocks (FIR/IIR, FFT)

Designed High Speed Serial Link (6 GHz) using 65nM technology (IBM) Designed CACHE controller (MESI and MOESI) for MPU. Designed cryptography units (DES, 3DES, DESX, SHA, AES) CAE EXPERTISE AND TOOLS

Tools: PowerArtist, tcl, shells, awk/sed/perl, python, make, C, C++ Languages: Verilog, SystemVerilog, VHDL, SVA, PSL

Synopsys: VCS, Verdi, DC, PrimeTime, TetraMAX, Formality, VCS, MVSIM, MVRC, Spyglass, VC LP

Cadence: Incisive NC, vManager, Incisive Formal (LEC), Conformal LP, JasperGold, IMC Mentor: ModelSim, Questa, Fastscan, Formal PRO (LEC) EDUCATION

MS E.E. Odessa National Polytechnic University, Odessa, Ukraine US CITIZEN

2/2022 - 3/2023

Google, Mountain View, CA

Verification Consultant

Verified the Power Management (PCU) and Clock Management (CCU) IPs

(blocks) using UVM, SystemVerilog

Verified the "Measurement and Analysis" IP block

Worked to improve coverage for DFT and Functional modes 11/2021 - 4/2022

JAD Enterprises, CA

Pr. Verification Consultant

Developing verification environment for the Crypto block Debugged X-prop using GLS for high speed SOC (multiple clock & power domains) Developed UVM based “double agent” verification environment for SOC 5/2021-11/2021

Boston Scientific, Minneapolis, MN

Sr. Verification Consultant

Designed a verification environment (UVM) for the new generation of ICE Run gatesim for audio control block

Blocks integration into SOC level using UVM

7/2020-2/2021

HW Start up at the stealth mode

Pr. Designer/Verification Engineer

Designed low power RTL for crypto blocks: AES (128 & 256), SHA2. Designed a verification environment (UVM) from scratch. Verified different DMA blocks using UVM (Questa).

Traced bugs to the RTL

Set up regression for SOC and SOC.

9/2019 – 5/2020

Tesla Motor, Palo Alto, CA

Pr. Verification Consultant

Wrote and maintained UVM's verification Components and Objects: Drivers, Monitors, ScoreBoards, Sequence_items, Sequences, and Virtual Sequences (CRV based) Designed verification environment for the new multicore system (RISC V) using UVM/SystemVerilog

Wrote test plans using vManager (Cadence). Traces bugs to the RTL Identified corner cases and wrote stimuluses to achieve coverage goal/correctness Wrote functional coverage covergroups for the interfaces and monitors (UVM) Wrote assertions (SVA) for 'assert' and 'cover' using binding files Developed environment for the DFT (JTAG) verification (MBIST, LBIST) Wrote multiple python scripts to generate stimuluses (TCL) for the errors' injection Developed Python based monitors for the regression after random error injection Used Jenkins tool for the Continuous integration and JIRA for the bugs/issues tracing 4/2019 – 8/2019

Recursion Dynamics, Odessa, Ukraine

Pr. Verification Consultant/Lead

Set up remote offices for the ASIC design and verification activity Developed from scratch framework for the functional verification using UVM directory tree, basic components and objects

Performed Logical Equivalence Check and Sequential Logic Equivalence Check (Jasper) Set up verification process for the RTL design

5/2018 – 3/2019

Synaptics, CA

Sr. Verification Consultant

Performing verification IOT block using UVM

Triaged regression failures and make testbench updates Wrote assembly and macro assembly scripts for functional coverage for the superscalar processor

Debugged functional errors in RTL using simulation and debug tools (Verdi) Developed verification environment for CPU testing Wrote coverage scripts

Trace the issues to the RTL

1/2018 – 5/2018

Broadcom, CA

Sr. Verification Consultant

Designed mixed signal verification environment using UVM Debugged RTL code

4/2017-12/2017

JAD Enterprises, CA

Pr. Engineer

Provided technical management for the distributed verification team (four engineers) Designed UVM based verification environment from scratch Developed comprehensive UVM based IPs’ verification methodology Designed Low Power aware verification strategy

1/2017-4/2017

Lockheed Martin, CA

Sr. Consultant

Developed verification environment (UVM) for the space-based telecommunication calibration unit.

Designed verification components for the FPGA based system 5/2016-12/2016

HGST (Western Digital), CA

Sr. Consultant

Developed verification environment (UVM) for SSD (DWL) block from scratch. Designed verification environment for security control module (SHA, AES128) Developed UVM base components for AXI4-lite and AXI4 slave interfaces. Wrote RTL for the PCIe 3.1 PIPE-PMA (SerDes) for the low-power device Developed UVM based environment for DDR3 performance optimized controller (partially used Cadence VIP). Translated old vera scripts to the SystemVerilog 7/2015-5/2016

JAD Enterprise, CA

Sr. Principal Engineer

Developed verification methodology and scripts for low power SOCs (Arm/Cortex) based on UVM (SystemVerilog) and IEEE-1801-2013 standard (UPF2.1) Designed verification environment (UVM) for high speed memory controllers (DMA) Optimized UVM scripts for migration from UVM1.1 to UVM1.2 to reduce simulation time for VCS environment

Closed coverage measures to identify verification holes and to show progress towards tape-out 3/2014- 7/2015

Atmel Corp, San Jose, CA

Sr. Staff Engineer

Wrote SVA scripts for functional verification and coverage Build effective constrained random verification environments from scratch. Developed memory block’s verification environment using UVM. Wrote CRV script for regression and functional verification (UVM) Designed verification scripts to improve coverages (code and functional) Developed DDR3 controller’s verification using UVM 7/2012- 1/2014

JAD Enterprise, San Jose, CA

Verification Consultant

(Samsung, Synopsys, Xilinx, Altera)

Developed methodology for low power devices' verification Verified Low Power Design using MVSIM and MVRC, wrote UPF scripts for low power verification and synthesis.

Developed UVM based ‘Power Centric’ verification for the clock-gating, MVMF, and Power Domain based designs

Wrote agents (UVM) for USB3 verification (Reconfigurable IP) Developed verification environment for Journal Engine (SSD) Verified Multiprocessor Memory switch using UVM1.1 Rewrite Verilog-A mix signal models using SystemVerilog (wreal) and DPI (C++) 4/2011-6/2012

Sandforce/LSI San Jose, CA

Principal ASIC Engineer

Developed verification environment for reconfigurable write channel using UVM (1.0ea) Designed agents (UVM), and UVM verification related classes: scoreboard, env, virtual sequence and sequencer using Cadence environment.

Wrote scripts for register layer modeling using RDL (Register Description Language) and UVM_RGL.

2005 - 2011 San Jose, CA

Consultant (Microsoft/Canesta, Synaptics, Verayo, AMD, IBM, Qualcomm) Verified 3D processing block using DPI (Questa) and OVM Wrote SVA script for error detection and functional coverage Developed verification environment using NC Incisive (Cadence) and OVM Wrote test suites for ARM using AXI/APB/AHB interface using Questa (AVM) Designed verification system for Ethernet using Vera (RVM) and SystemVerilog Wrote SystemVerilog assertions (SVA) for functional coverage Developed verification environment for the router blocks using Vera Designed low power communication products, reduced dynamic power up to 30% Designed verification environment for PCI interface (Xilinx Spartan 2 XC2S15) Designed high speed serial link modules using 65 nM technology (VHDL) Validated performance. Wrote models for mix-signal simulation Developed verification environment and constraints for ECC verification using different statistical models for error insertions

1998- 2005

JAD Enterprise Consulting San Jose, CA

Sr. Engineer/Project Lead

Designed Verilog/SystemVerilog/Superlog models for Viterbi and Turbocode based communication blocks.

Designed Cache Coherency protocol checkers.

Wrote assertions for functional coverage-based verification Verified PCI-E control block (DMA) using System Verilog VMM Modeled external interfaces using SystemVerilog (NC Incisive). Designed high speed channels and cache control block (MESI) Developed block and system level testbenches for cryptography using Vera. Designed low-power systems for wireless devices

Verified hardware encryption protocols: DES, 3DES, AES, SHA, ECC Designed pixel manipulation module for 3D graphic using Module Compiler 1996 - 1998

Philips San Jose, CA

Sr. Design Engineer

Designed XA controller and serial communication controller’s systems/units for 16 bit microcontrollers (I2C, SDLC/HDLC, and byte oriented protocols) Wrote Verilog and VHDL scripts for synthesis and verification Developed T1/E1 interface units for communication systems Designed video compression DCT (Discrete Cosine Transform) block Designed MPEG2 system for video-on-demand

Verified high speed video compression block

Manage of the international team of ASIC designers. Designed multiple processors and interface blocks

Verified adaptable interface block for the SPARC workstations

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