Professional Summary

*years * month of experience in the field of ASIC Design and verification in the semiconductor industry.

Seeking an Engineer position that enables me to utilize my skills within the field to make a positive contribution to the company.

Technical Skills Set/Tools

Strong knowledge of AMBA AHB, AXI, PCIe, USB3.0, PIPE transceiver (USB3.0), xHCI, AHCI, NVMe1.1b, Nvme1.2, SPI, I2c, I3c, USB2.0.

Good Knowledge of Mixed-signal concepts of digital and analog signals on the IC.

Understanding of semiconductor fabrication process, and semiconductor devices.

Serializer- Deserializer (SerDes), clock and data recovery (CDR) circuits, and phase-locked loop (PLL) or other timing circuits.

Ideally, strong experience in USB3.0 Layer (PHY), including protocols.

Good IP knowledge in some PHY blocks PCIe

Familiar with VHDL, Verilog, familiar with VHDL, Verilog, C and C++, System Verilog, and assembly language and a python script.

Sound knowledge in test cases, SOC simulation, and UVM methodology.

Solid understanding of developing system-level test cases and ASIC Design Flow.

Tools knowledge in Verdi (Simics), Modelsim, Questa-sim.

Participated in the training of Metric Driven Verification given by Cadence.

Experience in silicon bring-up and debugging.

5+ years of experience in RTL design and Verification.

3+ years of Pre-SI verification work using a validation methodology UVM with SOC /IP development.

Project Experience

1.Senior Verification Engineer, February 2022 to September 2022

UST Global, USA (Client – Intel Folsom, USA)

I have worked with the unified emulation and prototype system ZeBu (Synopsys) and hybrid VCS models that utilize MCF emulation models.

Experience with FPGA SoC architectures of this MCF environment and discover with FPGA design to understand and report RTL bugs to development team.

Used TREX command to configure loopback connectivity for the HESE I3C/I2C ports during runtime. The UTMI interface on the USB device controller is directly connected to the USB transactor, while the PPI interface on the CSI host controller is directly connected to the CSI transactor.

Created test cases utilizing.bin files by using trex command in the switches of Host Engine, Security Engine and Vision Engine (ULPV)

Override/update any of the firmware images; tested SV Firmware loading; passed in the switch -ms -ms- Copy the override from the model, and as necessary, update the.bin files.

Used Best Known Configuration (BKC) models for each release and sent emails with revised test contents to the team.

Worked on various SPI complete boot tests, UART (HE and SE) cycle lists, SPI HE Cycle lists, Vault rom bring up tests (ZEBU model, EP1 model), lch reset b tests, 2-bit ECC correction, and 5-bit ECC corrections tests.

Used Verdi commands to analyze test-case log files and debug depending on test scenario with replay waveform. Notified the team of RTL with Verilog code and firmware related bugs.

Used C++, Python, C to integrate the test and verified with UVM functional coverage assertions to get the good coverage.

2.Senior Engineer, September 2015 to March 2016

Mobiveil Technologies India Pvt Ltd, Chennai (Client – Synopsys (US))

Developed Test Environment and Sequences.

Enhancement of UVM Environment / Test-cases for supporting various scenarios (Randomization).

Debugged Test-cases and reported issues. involves developing the test layer and finding out bugs in both NVMe Host VIP and NVMe Controller VIP.

Achieved functional, code coverage

Used C++, System verilog,verilog to integrate the test and verified with UVM functional coverage assertions to get good coverge.

Achieved register read write using PCIe with Nvme controller VIP.

3.Verification Engineer, September 2013 to August 2015

Mobiveil Technologies India Pvt Ltd, Chennai (Client – Marvell (US))

Understanding and various rules of TRB cache DUT.

Enhancement of UVM Environment / Testcases for supporting various scenarios (Randomization).

Understanding and various rules of TRB cache DUT.

Developed Test Environment and Sequences.

Debugged Test-cases and reported issues.

Developed Functional Coverage Subscribers and modeled complete XHCI software behavior, in order to exercise maximum possible scenarios and achieve coverage and Achieved functional using system Verilog assertions, code coverage .

Educational Summary

B.E (Computer Science) with 84% from Kings Engineering College – Anna University, Chennai (2006 – 2010)

I hereby certify that above - provided information is true to the best of my knowledge.

Date: 09/09/2023 Sankareswari Ponnambalam.

Contact this candidate