Peter Park

Senior Verification Engineer - Displays

Email) ad3fdq@r.postjobfree.com

Tel) 207-***-****

Senior Verification Engineer Qualifications

Expertise in digital camera video/image processing pipeline design

Extensive knowledge and experience with UVM advanced verification methodology

Familiar with UVM testbench and functional coverage, such as SVA and Covergroup.

Familiar with verification plan and coverage metrics

Familiar with OOP constructs and constraint random verification

10+ years of experience with FPGA design and implementation, including verification, synthesis and P&R, STA, timing analysis and closure.

Experience with Intel Quartus II and Xilinx Vivado and FPGA devices.

Excellent Verilog/SystemVerilog, VHDL RTL coding skill

Extensive working knowledge of digital logic, analog circuit and mixed-signal design

Proficiency in C, Matlab/Simulink and Python programming

Working knowledge of Vitis HLS

Experience with AXI4-Steream, AXI4 Memory Mapped, AXI4-Lite

Experience with Jira/Jama and version control tools

Familiar with highspeed serial interfaces, such as USB, SPI, i2c, GigE and PCIe

Self-motivated individual with excellent work ethics and a “can-do” attitude

Proven experience working in a high-pressured, deadline-driven environment.

Work well in a dynamic team environment as a team player

Strong problem-solving skills and attention in detail

Strong written and verbal communication and technical documentation skills

Professional History

Technical Consultant (2023.7 – present)

EdgeSoft Inc, located in Seoul Korea

Provided consulting service for camera ASIC/FPGA design, including advanced verification methodolody, such as UVM, SVA and Covergroup as functional coverage.

Remotely working as contract base

Principal Design/Verification Engineer (2021. 10 - 2023.6)

On semiconductor, located in South Portland, ME

Developed/verified power management ICs.

Developed UVM test bench and SVA, Covergroup

Developed DFT with Synopsys TetraMax

Familiar with UVM and SVA, coverage

Familiar with verification plan and coverage metrics

Technical Consultant (2016. 2 – 2021.9)

EdgeSoft Inc, located in Seoul Korea

Provided consulting service for ASIC/FPGA design, including verification.

Consult with advanced verification methodology, UVM.

Remotely working from Canada

Sr. FPGA/Digital Design Engineer (2013. 7 – 2016.1)

Allied Vision Technologies Inc. Machine-vision camera manufacturer

Developed machine vision camera with Altera/Xilinx FPGA

Developed camera subsystem and test-bench with VHDL or SystemVerilog/UVM

Sustained/enhanced legacy design data.

Sr. FPGA/Digital Design Engineer (2011 – 2013)

Dynawave Technology Inc, a start-up for video converter development in North Vancouver

Developed HD-SDI satellite video converter using FPGA.

Verified H.264 Encoder for full HD-SDI converter.

FPGA Image Processing Engineer (2010)

Point Grey Research Inc., Digital Camera Manufacturer, Richmond, BC, Canada

Enhanced and verified image processing legacy data

Tested image quality using FPGA emulator.

Developed noise reduction, such as a median filter design to enhance image quality.

Sr.FPGA/ Digital Design Engineer (2006 – 2010)

Cantronics Systems, Inc – Coquitlam, BC. Infrared camera system manufacturer

Developed FPGA for embedded infrared camera using thermal sensors.

Designed PIC and ARM9 based embedded system for Infrared camera.

Lab with oscilloscope and logic analyzer, multi-tester for test and debug

EDUCATION & TRAINING:

Master degree of Electronic Engineering, Yonsei University, Korea

References available upon request.

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