| Resume alert | Resumes 41 - 50 of 67 |
Design Engineer
Pune, MH, India
... > Experience in writing RTL models in Verilog, VHDL and Test benches in System Verilog. > Good knowledge in verification methodologies. > Experience in using industry standard EDA tools for the front-end design and verification. VLSI Domain Skills: ... - 2014 Dec 19
... > Experience in writing RTL models in Verilog, VHDL and Test benches in System Verilog. > Good knowledge in verification methodologies. > Experience in using industry standard EDA tools for the front-end design and verification. VLSI Domain Skills: ... - 2014 Dec 19
Project Engineering
Pune, MH, India
... TECHNICAL SKILLS * C, C++,OS, MICROCONTROLLER, VHDL & VERILOG, MATLAB, VLSI, ALP,CCNA. * Technical Paper Presentation on MAGNETIC RAM. SOFT SKILLS * Tentative, Leadership, Strong, Willpower, Motivation, Punctuality. * Willing to Relocate any where ... - 2014 Oct 18
... TECHNICAL SKILLS * C, C++,OS, MICROCONTROLLER, VHDL & VERILOG, MATLAB, VLSI, ALP,CCNA. * Technical Paper Presentation on MAGNETIC RAM. SOFT SKILLS * Tentative, Leadership, Strong, Willpower, Motivation, Punctuality. * Willing to Relocate any where ... - 2014 Oct 18
Project Engineer
Pune, MH, India
... Technical Proficiency • Experience in VHDL, Verilog, Xilinx Spartan FPGA programming. • Expertise in Synthesis, Place & Route, Static Timing Analysis. • Proficiency in RTL design, MAT LAB, simulation and synthesis using Xilinx ISE tools. • Highly ... - 2014 Sep 21
... Technical Proficiency • Experience in VHDL, Verilog, Xilinx Spartan FPGA programming. • Expertise in Synthesis, Place & Route, Static Timing Analysis. • Proficiency in RTL design, MAT LAB, simulation and synthesis using Xilinx ISE tools. • Highly ... - 2014 Sep 21
b.tech (ece)
Pune, MH, India
... Shridhar University,Pilani 2014 7.6 XII (U.P.) Ram Dev Janta Inter College, 2009 59.2 % Katheri X (U.P.) Janta Inter College, 2007 66.0 % Maharuwa TECHNICAL SKILLS Software/Hardware Languages C, Verilog Software Xilinx ISE, Cadance, Matlab,Keil ... - 2014 Sep 16
... Shridhar University,Pilani 2014 7.6 XII (U.P.) Ram Dev Janta Inter College, 2009 59.2 % Katheri X (U.P.) Janta Inter College, 2007 66.0 % Maharuwa TECHNICAL SKILLS Software/Hardware Languages C, Verilog Software Xilinx ISE, Cadance, Matlab,Keil ... - 2014 Sep 16
Engineer Project
Pune, MH, India
... Skills & Abilities Hardware Description Languages: Verilog, VHDL Software Programming Languages: C, C++, Embedded-C/C++, Assemble level Language, Shell Programming, Python. GUI Library: OpenCV, SimpleCV, Pygame, Matplotlib, Debugging tools: GDB, ... - 2014 Aug 19
... Skills & Abilities Hardware Description Languages: Verilog, VHDL Software Programming Languages: C, C++, Embedded-C/C++, Assemble level Language, Shell Programming, Python. GUI Library: OpenCV, SimpleCV, Pygame, Matplotlib, Debugging tools: GDB, ... - 2014 Aug 19
Project Engineering
Pune, MH, India
... PROFICIENCY IN PROGRAMMING: • Verilog Programming Language, good. • TCL Scripting, good. • Shell Scripting, fair. • System Verilog Programming Language, Beginner. • C Programming Language, good. • C++ Programming Language, Beginner. TOOLS USED: ... - 2014 Jun 26
... PROFICIENCY IN PROGRAMMING: • Verilog Programming Language, good. • TCL Scripting, good. • Shell Scripting, fair. • System Verilog Programming Language, Beginner. • C Programming Language, good. • C++ Programming Language, Beginner. TOOLS USED: ... - 2014 Jun 26
Fresher in electronics and communication Engineering
Pune, MH, India
... Skill Sets Languages : C++, ALP, VHDL/ Verilog, Matlab Operating System : Windows 7, Windows XP, Windows 8 Technical Activities Attended the pre-placement training organized by department of placement and training at SMVITM Bantakal. Attended the ... - 2014 Jun 20
... Skill Sets Languages : C++, ALP, VHDL/ Verilog, Matlab Operating System : Windows 7, Windows XP, Windows 8 Technical Activities Attended the pre-placement training organized by department of placement and training at SMVITM Bantakal. Attended the ... - 2014 Jun 20
Design System
Pune, MH, India
... quickly and utilize them in an effective manner TECHNICAL PROFICIENCY Operating Systems: LINUX Red Hat, WINDOWS Languages: Verilog, SystemVerilog, PERL(Beginner), SystemC Methodology: UVM Methodology Bus protocols: AMBA-AHB, PCI Physical layer ... - 2014 Jun 12
... quickly and utilize them in an effective manner TECHNICAL PROFICIENCY Operating Systems: LINUX Red Hat, WINDOWS Languages: Verilog, SystemVerilog, PERL(Beginner), SystemC Methodology: UVM Methodology Bus protocols: AMBA-AHB, PCI Physical layer ... - 2014 Jun 12
verilog,system verilog,universal verification methodology
Pune, MH, 411046, India
... 68.00% Science, Wardha Agragami High Maharashtra S.S.C School, Wardha State Board 2004 73.86% SOFTWARE SKILLSET HDL and HVL Verilog, System Verilog Methodology Universal Verification Methodology(UVM) ASIC Design XILINX and Questasim Software tools ... - 2014 May 28
... 68.00% Science, Wardha Agragami High Maharashtra S.S.C School, Wardha State Board 2004 73.86% SOFTWARE SKILLSET HDL and HVL Verilog, System Verilog Methodology Universal Verification Methodology(UVM) ASIC Design XILINX and Questasim Software tools ... - 2014 May 28
VLSI
Pune, MH, India
... > VLSI Programming Languages : VHDL, Verilog HDL. > Layout Tools : SPICE. > VLSI Programming Tools : Xilinx, QUESTASIM. > FPGA : Vertex-4. > Languages : C, core java. ACADEMIC PROJECT (PG-DVLSI): TITLE: FPGA implementation of Transmission Control ... - 2014 May 12
... > VLSI Programming Languages : VHDL, Verilog HDL. > Layout Tools : SPICE. > VLSI Programming Tools : Xilinx, QUESTASIM. > FPGA : Vertex-4. > Languages : C, core java. ACADEMIC PROJECT (PG-DVLSI): TITLE: FPGA implementation of Transmission Control ... - 2014 May 12