Design Engineer

Deepak Kawathale

Flat No.***, B.G Apartment,

Maling Road, Aundh,

Pune - 411007

Email:******.*********@*****.***

Mobile: +91-770*******

Objective:

Seeking a position in a challenging environment, where I can apply my

skills and grow professionally by being resourceful, innovative and

flexible.

Summary of Qualifications:

> Good understanding of the ASIC and FPGA design flow.

> Experience in writing RTL models in Verilog, VHDL and Test benches in

System Verilog.

> Good knowledge in verification methodologies.

> Experience in using industry standard EDA tools for the front-end

design and verification.

VLSI Domain Skills:

HDLs : Verilog, VHDL

HVL : SystemVerilog

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification

TB Methodology: OVM

EDA Tool : Modelsim and ISE14.1, Questa,Matlab

Domain: ASIC/FPGA Design Flow, Digital Design

methodologies

Knowledge : RTL Coding, FSM based design,

Simulation,

Code / Functional Coverage,

Synthesis, C, Microcontrollers

Experience Summary:

VLSI Freelancer at Idea Maps, Pune

Year: May 2014 - Present

VLSI Design Engineer at Qualitat System, Pune

Year: October 2013 - April 2014

VLSI Design Engineer at Saitech Solutions, Pune

Year: April 2013 - October 2013

Maven Silicon Certified Advanced VLSI Design and Verification course from

Maven Silicon VLSI Design and Training Center, Bangalore

Year: September 2012-February 2013

Paper Presentations and Achievements:

> 4th university topper in engineering

> A technical paper presented on "Traffic controlling using RFID" at

Radhikatai Pandav College of engineering, Nagpur.

Career Path & Academics:

> B.E in Electronics Engineering (2012) from J D college of Engineering,

Nagpur (Nagpur University) with 74.36% aggregate.

> Pre-University Education (2008) from M B Science College, Latur

(Maharashtra State Board) with 60.64%of Marks.

> SSLC (2006) from Lal Bahadur Shastri Vidyalaya, Latur (Maharashtra

State Board) with 77.48% of Marks.

1 Projects Undertaken:

During Working:

At Idea Maps:

Title: Implementation of process scheduling strategies of operating systems

using FPGA

HDL: Verilog

EDA Tools: ISE 14.1 and Modelsim

Description: The main objective of the project is the hardware

implementation of multitasking strategies using VHDL/ Verilog on FPGA.

Multitasking strategies include Multitasking mode, Round Robin mode, and

Request/acknowledgement mode. Three different devices like GSM modem, RFID

reader and Keypad are connected to FPGA. Three different tasks are executed

in different modes. The inputs from Keypad is displayed on seven segment

display interfaced to FPGA, the message received by the GSM Modem is

displayed on LCD display interfaced to FPGA and the unique identification

number (UIN) of smart cards are read by the RFID reader and displayed on

the LEDS connected to the FPGA board. When all the tasks are running

simultaneously it is in multitasking mode, whereas in Round Robin mode each

task is assigned some priority, Based on the priority each task will run

for certain interval of time later it is preempted and the other tasks

starts running. In Request/acknowledgement mode, the application which

requests for the service is served and all other tasks are ignored.

At Saitech Solutions:

Title: Design and Implementation of CORDIC processor for Complex DPLL

Duration: 2.5 months

HDL: Verilog

EDA Tools: Modelsim, ISE 14.1 and Isim

Description: Coordinate Rotation Digital Computer (CORDIC) algorithm has

turned out to be such kind of programmable signal processor. In recent

times, it has been a widely researched topic in the field of vector rotated

Digital Signal Processing (DSP) applications due to its simplicity. This

paper presents the design of pipelined architecture for coordinate rotation

algorithm for the computation of loop performance of complex Digital Phase

Locked Loop (DPLL) in In-phase and quadrature channel receiver. The design

of CORDIC in the vector rotation mode results in high system throughput due

to its pipelined architecture where latency is reduced in each of the

pipelined stage. For on-chip application, the area reduction in proposed

design can is achieved through optimization in the number of micro

rotations.

Title: Design and Implementation of 16 bit RSIC Processor

Duration: 2 months

HDL: Verilog

EDA Tools: Modelsim, ISE 14.1 and Isim

Description: In this project, we proposed a 16 bit non-pipelined RISC

processor which used for signal processing applications. The processor

consists of blocks namely, program counter, control unit, ALU and

registers. A high speed and low power modified multiplier designed in the

ALU. The RISC processor has been designed for executing 27-instructions

set. It is expandable up to 32 instructions, based on the user

requirements.

At Qualitat Systems:

Title: FPGA implementation of encryption, decryption & Key generation for

AES algorithm

Duration: 2 months

HDL: VHDL, Verilog

EDA Tools: Modelsim, ISE 14.1 and Isim

Description: AES is an acronym stands for advanced encryption standard

which is based on the design principle of substitution permutation

network.AES is a variant of Rijindael which has fixed block size of 128

bits where 10 cycles of repetitions are needed and most of the calculations

are done in a finite field called as Galois field. Plaintext and cipher

text are taken as input for key gen and key out is taken. The main

algorithm is divided into 4 parts mainly key expansion, initial round,

rounds and final round. The rounds are further divided into sub-

bytes,shiftrows,mix column and add round key and therefore sbox and inverse

s box taken into consideration. Finally the o/p has been observed and it

has been implemented on FPGA.

Title: Design and Implementation of High Performance AHB Reconfigurable

Arbiter for on chip Bus Architectures

Duration: 2.5 months

HDL: VHDL, Verilog

EDA Tools: Modelsim, ISE 14.1 and Isim

Description: Resolution is a big issue in system on chip while dealing with

number of masters trying to sense a single data bus. This paper presents

the Design and Simulation of a typical High Performance AHB Reconfigurable

Master for on chips Bus Architecture using verilog HDL. In this methodology

I here used wrap logic to generate data at specific time by several bus

masters. The key point in this paper is wrap logic. The FSM forAHB master

has been generated & simulated on modelsim HDL tool. The scheme involves

several AMBAfeatures of pipelined operation, multiple bus masters, burst

transfers, split transactions. The purpose of this paper is to propose a

scheme to implement reconfigurable architectures so that it can be

interfaced with anyIP core as such a system using AMBA bus specification.

Here we proposed generation of AMBA ABH master using wrap logic. The design

architecture is written usingVerilog HDL using Modelsim tool. The timing

diagrams are also generated on this tool.

Title: Design and FPGA Implementation of 2-D FFT Processor using Radix-2,

Radix-4 and split radix algorithm

Duration: 2 months

HDL: VHDL, Verilog

EDA Tools: Modelsim, ISE 14.1 and Isim

Description: The 2-Dimensional (2-D) FFT is a fundamental, computationally

intensive function that is of broad relevance to multidimensional signal

processing computation, such as those found in smart camera system, medical

imaging tools and other important applications. The2-D FFT is typically

implemented as repeated invocations of 1-Dimensional (1-D) FFTcomputations

[3]. Therefore, techniques for efficient FPGA based 2-D FFT computations

can be derived by considering two key design issues primarily by improving

the throughput of 1-D-FFT computation with efficient FPGA resource

utilization and secondly by carefully utilizing the limited bandwidth of

data transfer between the targeted FPGA device and external memory. Since 2-

D FFT computation consists of 1-D FFT computations, the throughput of 1-D

FFT computation directly influences that of the enclosing 2-D FFT[4]. A

systematic method for improving the throughput of 2-D FFT implementation by

parallel implementation of 2-D FFT on FPGA has been developed in reference

[9]. It has been reported that this method achieves virtually linear speed

up and real time performance for large matrix sizes. Improvement in VLSI

implementation focuses mainly on power, speed and area.

During Training:

Title: Real Time Clock - RTL Design and Verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa - Verification Platform and ISE

> Implemented the Real Time Clock using Verilog HDL independently

> Architected the class based verification environment using

SystemVerilog

> Verified the RTL model using SystemVerilog.

> Generated functional and code coverage for the RTL verification sign-

off

DECLARATION:

I hereby declare that the above mentioned details are

correct to best of my knowledge. I am also confident to suffice all needs

as a team player.

Place: PUNE

Date:

Deepak Kawathale

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