JAYAKIRTHI REDDY

Email: acejlj@r.postjobfree.com Phone: (M) +91

988-***-****

House No: 68, 2nd Cross, Mathru Layout, GKVK post, Yelahanka Newtown,

Bangalore, Karnataka -560065

To work in a quality environment that will serve as a platform to learn

and enhance my professional skills, where acquired skills and

education will be utilized towards growth and advancement of

organization

Young, energetic and result-oriented M.S (VLSI System Design and

Verification) & B.E (Electronics & Communications) professional

offering 1year of experience as Intern in Semiconductor/VLSI/EDA

Demonstrated excellence in tackling the issues related to Functional

Verification, Digital Design &

Verification

Experienced professional with superior ability to motivate personnel

and enhance the overall efficiency, performance, and compliance with

standard procedures and regulations

Excellent interpersonal and man-management skills with the ability to

handle multiple projects and motivate large cross-functional teams

Excellent communication, presentation, interpersonal and problem

solving skills with proficiency in grasping new technical concepts

quickly and utilize them in an effective manner

TECHNICAL PROFICIENCY

Operating Systems: LINUX Red Hat, WINDOWS

Languages: Verilog, SystemVerilog, PERL(Beginner), SystemC

Methodology: UVM Methodology

Bus protocols: AMBA-AHB, PCI Physical layer

Simulators: VCS, NCSIM

Areas of Expertise

Digital Design SystemVerilog

UVM IP & SOC Verification

PROFESSIONAL CONTOUR

Whizchip Design Technologies, Bangalore (Jul '12 - Jun '13)

Post Graduate Intern

Key Deliverables:

Creating Verification Environment for IP's in SV -UVM Environment

Responsible for formulating Testcases

for the IP's

Inspecting Functional Coverage and achieving 100% coverage

Reporting the functionality of IP's

Key Achievements:

Successfully developed Verification Environment for IP's

Successfully designed Elastic buffer in

SC

Wrote Testplans

Projects Handled:

High Speed Serial Communication between SV Environment and SC Design

Location: Whizchip Design Technologies, Bangalore

Duration: Jul '12 - Jun '13

Environmen UVM, SystemVerilog, SystemC

t:

Descriptio Verification Environment is to mimic the physical layer (PCS)

n: developed environment of standard

communication protocol such as PCIe using SystemVerilog, UVM. SystemC

module consisting of clock

recovery circuit and Elastic buffer is designed. SystemVerilog

and SystemC module is used in a single hardware/software

simulation which allows using both languages' strengths. After

creating an environment, connection is established between

SystemVerilog-UVM module and SystemC at signal level by sending

an Encoded serial data from the SV-UVM side to SystemC side

with a jittery clock. Data is Encoded using 8B/10B encoding

technique. Jittery clock is used to mimic real time

environment. The data received at the receiver end is

synchronized to the local clock domain to

Compensate frequency drift between recovered clock (jittery

clock) and local clock. Elastic buffer is implemented to

synchronize the drift between the two different clocks.

Key Deliverables:

Creating verification environment in UVM Methodology

Design of Blocks in SystemC

Involved in developing Test cases

OCX- Data Transfer Protocol

Languages: Verilog

Description: Design of receiver module which receives data from 8bit

data bus depending on control signal as input and transfer 512

bit data output along with other control signals as output.

Design of transmitter module which accepts 512 bit data as

input depending on control signal and transmit data from 8 bit

port along with other control signal.

Timing Parameters Checking in SystemC

Languages: SystemC

Description: A module is developed to check Timing parameters like

Setup, Hold, recovery, removal and pulse width in SystemC .

When a timing violation occurs, run time option is given to the

user to take action on affected signal.

EDUCATIONAL CREDENTIALS

M.S (VLSI System Design and Verification) from MCIS, Manipal

University in 2013 with 8.57 CGPA B.E (Electronics & Communications)

from VTU, Belgaum in 2009 with 64.5%

PUC from Nagarjuna PU College, Karnataka Pre-University board in 2005

with 78.3%

X from Govt. Junior College, Karnataka state board in 2003 with 64%

ACADEMIC PROJECTS

Design and Verification of 8 bit ALU

Languages: Verilog,UVM

Tools: VCS

Description: An 8 bit ALU is designed in Verilog for arithmetic and logical

operations. Verification of ALU

is done by creating a verification environment using System Verilog

UVM methodology and

checked for all the testcases.

Design of an Asynchronous First in First out (FIFO)

Language: Verilog

Tools: VCS

Description: Design of an asynchronous FIFO which is used to synchronize two

different modules working

at different clock frequencies with the help of synthesis techniques

described in SNUG

Papers

Extra-Curricular Activities

Represented College/School in Inter-College Cricket and Badminton

tournaments as a Captain Participated in a Science Fairs, Math and

General Knowledge competitions at the School & District level

PARTICIPATIONS

Attended Wireless Telecom training conducted by Nano Cell networks

Attended 2 day workshop on Cadence tools conducted by Cadence at

MCIS, Manipal

Date of Birth: 20th Jan, 1988 Sex: Male Languages Known:

English, Kannada, Telugu and Hindi

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