| Resume alert | Resumes 61 - 67 of 67 |
M.Tech in Information Technology Curriculum Vitae
Pune, MH, 444057, India
TUSHAR C WANKHADE International Institute of Information Technology,P-14, Rajiv Gandhi InfoTech Park, Hinjewadi, pune, Maharashtra 444501 Phone: +919********* Cell: +919********* E-Mail: vx6ho4@r.postjobfree.com Skills Languages: C, C++, Verilog, ... - 2012 Jul 28
TUSHAR C WANKHADE International Institute of Information Technology,P-14, Rajiv Gandhi InfoTech Park, Hinjewadi, pune, Maharashtra 444501 Phone: +919********* Cell: +919********* E-Mail: vx6ho4@r.postjobfree.com Skills Languages: C, C++, Verilog, ... - 2012 Jul 28
Project Design
Pune, MH, 411034, India
... Tools : • Design Architect by Mentor-graphics • RTL Compiler (front end) , SOC Encounter (back end) by Cadence • Xilinx ISE 12.3i • Plan Ahead Xilinx 12.3i Languages : Verilog, VHDL. Operating Systems : LINUX, Windows. ASIC Design. FPGA. Digital ... - 2012 Jun 19
... Tools : • Design Architect by Mentor-graphics • RTL Compiler (front end) , SOC Encounter (back end) by Cadence • Xilinx ISE 12.3i • Plan Ahead Xilinx 12.3i Languages : Verilog, VHDL. Operating Systems : LINUX, Windows. ASIC Design. FPGA. Digital ... - 2012 Jun 19
High School Project
Pune, MH, 411024, India
... SKILLS : Language : VERILOG, VHDL, CMOS (Basics), ASIC (Basics), PCB Designing, C Language. Knowledge of : HDL synthesis, Static timing Analysis, Test Cases, Advance Digital Design. PROJECTS : Project Title Description of the project Major(B.E) Road ... - 2012 Jun 19
... SKILLS : Language : VERILOG, VHDL, CMOS (Basics), ASIC (Basics), PCB Designing, C Language. Knowledge of : HDL synthesis, Static timing Analysis, Test Cases, Advance Digital Design. PROJECTS : Project Title Description of the project Major(B.E) Road ... - 2012 Jun 19
Design Engineer
Pune, MH, India
... Programming Languages: Verilog, VHDL, UNIX, C Projects in Wipro: • PMIC: Power Management Integrated Circuit (PMIC) for mobile application processors platforms with high feature integration in order to minimize system board area. It includes ... - 2012 Jun 14
... Programming Languages: Verilog, VHDL, UNIX, C Projects in Wipro: • PMIC: Power Management Integrated Circuit (PMIC) for mobile application processors platforms with high feature integration in order to minimize system board area. It includes ... - 2012 Jun 14
Project Manager
Pune, MH, 411027, India
... Familiar with verilog EMPLOYMENT: Around 9 years of Project Management [3 years services + 6 years products] experience that includes resource & performance management, project management, process management. Around 11 years of combined technical ... - 2012 May 31
... Familiar with verilog EMPLOYMENT: Around 9 years of Project Management [3 years services + 6 years products] experience that includes resource & performance management, project management, process management. Around 11 years of combined technical ... - 2012 May 31
vlsi,asic,fpga,verilog/ vhdl
Pune, India
... TECHNICAL SKILLS: Advanced Digital Design,VHDL,VERILOG,CMOS Layout designing,Basics of System Verilog, ASIC, CPLD, FPGA. TOOLS: Xilinx- ise 9.2-,Model- sim,Riviera-pro,Leonardo-Spectrum,Microwind(CMOS layout designing),Altium(pcb). INTEREST I don’t ... - 2012 Feb 13
... TECHNICAL SKILLS: Advanced Digital Design,VHDL,VERILOG,CMOS Layout designing,Basics of System Verilog, ASIC, CPLD, FPGA. TOOLS: Xilinx- ise 9.2-,Model- sim,Riviera-pro,Leonardo-Spectrum,Microwind(CMOS layout designing),Altium(pcb). INTEREST I don’t ... - 2012 Feb 13
Manager Engineer
Pune, MH, India
... Tools : Visual Basics 6.0 Languages : VHDL, VERILOG Design Technology : VLSI Tools : Xilinx for Synthesis, Modelsim Xe II v5.6e for Simulation. Hardware Exposure : Computer Assembling EXTRA CURRICULAR ACTIVITIES Presented a Seminar on ‘ ... - 2010 Oct 19
... Tools : Visual Basics 6.0 Languages : VHDL, VERILOG Design Technology : VLSI Tools : Xilinx for Synthesis, Modelsim Xe II v5.6e for Simulation. Hardware Exposure : Computer Assembling EXTRA CURRICULAR ACTIVITIES Presented a Seminar on ‘ ... - 2010 Oct 19