| Resume alert | Resumes 21 - 30 of 67 |
Test Cases Project
Pune, Maharashtra, India
... Verilog programming in Quartus. Projects Undertaken SQTL Project Title: Orange HRM Project Description: Orange HRM is a solution to provide cost effective system to Company’s Human resource. It stores detailed information of employees with different ... - 2018 Sep 24
... Verilog programming in Quartus. Projects Undertaken SQTL Project Title: Orange HRM Project Description: Orange HRM is a solution to provide cost effective system to Company’s Human resource. It stores detailed information of employees with different ... - 2018 Sep 24
Team Leader Training
Pune, Maharashtra, India
... 15 days training of VERILOG from SVITS. ROBOTICS and SMART ELECTRONIC under Engineering Project Camp held in SAIT. 1 day tutorial Workshop on INDUSTRIAL AUTOMATION at Arist Automation. 1 day industry visit at SCIENTECH Indore. Academic Achievements: ... - 2018 Aug 31
... 15 days training of VERILOG from SVITS. ROBOTICS and SMART ELECTRONIC under Engineering Project Camp held in SAIT. 1 day tutorial Workshop on INDUSTRIAL AUTOMATION at Arist Automation. 1 day industry visit at SCIENTECH Indore. Academic Achievements: ... - 2018 Aug 31
Fresher
Pune, Maharashtra, India
... Programming languages Embedded C, C, Verilog Operating Systems Windows, Linux. Software known LT-Spice, Proteus Pro, Xilinx, MATLAB, LabVIEW, Cadence Virtuoso, 4nec2, 20SIM. IDE Tools MPLAB X, Atmel Studio. Others Skills Communication, Presentation, ... - 2018 Aug 23
... Programming languages Embedded C, C, Verilog Operating Systems Windows, Linux. Software known LT-Spice, Proteus Pro, Xilinx, MATLAB, LabVIEW, Cadence Virtuoso, 4nec2, 20SIM. IDE Tools MPLAB X, Atmel Studio. Others Skills Communication, Presentation, ... - 2018 Aug 23
Hardware Design
Pune, MH, India
... Responsibilities Developed System architecture with the help of Industry experts Design and implementation of complete Hardware required for CPE Design review and optimization Designed and Simulated control Logic for FPGA in Verilog Driver and test ... - 2018 Feb 12
... Responsibilities Developed System architecture with the help of Industry experts Design and implementation of complete Hardware required for CPE Design review and optimization Designed and Simulated control Logic for FPGA in Verilog Driver and test ... - 2018 Feb 12
Engineering Technical
Pune, MH, India
... Technical Proficiency • Technical Proficiency: C, Embedded C, Verilog HDL, RTOS(uCOS-II), IoT, I2C, SPI, MODBUS, GPS, GSM/GPRS, Networking Protocol. • Tools/Platforms: Keil uVision, Matlab, Python, Xilinx ISE, Ngspice, Cadence Virtuoso, Arduino and ... - 2017 Dec 02
... Technical Proficiency • Technical Proficiency: C, Embedded C, Verilog HDL, RTOS(uCOS-II), IoT, I2C, SPI, MODBUS, GPS, GSM/GPRS, Networking Protocol. • Tools/Platforms: Keil uVision, Matlab, Python, Xilinx ISE, Ngspice, Cadence Virtuoso, Arduino and ... - 2017 Dec 02
graduate trainee engineer
Pune, MH, India
... SkillSets Core Knowledge : Microcontroller, Microprocessor,VHDL,Verilog. Language : CORE - JAVA, Adv.JAVA, Servlets, JDBC,C#. Frame Work : Hibernate. Operating System : Windows 2000/XP/windows7 Web Technologies : HTML, CSS,JavaScript. Strengths Work ... - 2017 Nov 16
... SkillSets Core Knowledge : Microcontroller, Microprocessor,VHDL,Verilog. Language : CORE - JAVA, Adv.JAVA, Servlets, JDBC,C#. Frame Work : Hibernate. Operating System : Windows 2000/XP/windows7 Web Technologies : HTML, CSS,JavaScript. Strengths Work ... - 2017 Nov 16
c, verilog HDL, assembly language for microcontrollrs
Pune, MH, India
... Programming Languages : C, VHDL, Basic Embedded C, ALP, Verilog HDL, Basic JAVA . Tools : Matlab,Keil, Xilinx ISE,Multism, Eclipse . WORKSHOPS &PRESENTATIONS Participated in Workshop on “ADVANCED ROBOTICS” at IIT Madras, 2013. Participated in ... - 2017 Jun 21
... Programming Languages : C, VHDL, Basic Embedded C, ALP, Verilog HDL, Basic JAVA . Tools : Matlab,Keil, Xilinx ISE,Multism, Eclipse . WORKSHOPS &PRESENTATIONS Participated in Workshop on “ADVANCED ROBOTICS” at IIT Madras, 2013. Participated in ... - 2017 Jun 21
Project Electronics
Pune, MH, India
... TECHNICAL SKILLS Programming C, TCL,VHDL and Verilog Programming Languages Simulation Tools LT spice, Xilinx ISE, Lab VIEW CAD Tools Cadence Virtuoso (6.1.4),Cadence SOC Encounter,ICC Synopsys. RF Tools HFSS,4NEC PCB Design Tools Orcad, PCB Express ... - 2016 May 05
... TECHNICAL SKILLS Programming C, TCL,VHDL and Verilog Programming Languages Simulation Tools LT spice, Xilinx ISE, Lab VIEW CAD Tools Cadence Virtuoso (6.1.4),Cadence SOC Encounter,ICC Synopsys. RF Tools HFSS,4NEC PCB Design Tools Orcad, PCB Express ... - 2016 May 05
Project Data
Pune, MH, India
... Implemented RTL module in Verilog & verified using System Verilog. Designed the class based verification environment using System Verilog. TOOLS : Cadence NCSIM LANGUAGE : System Verilog (HVL) METHODOLOGY : Constrained Random Verification 2. FLOW ... - 2015 Dec 28
... Implemented RTL module in Verilog & verified using System Verilog. Designed the class based verification environment using System Verilog. TOOLS : Cadence NCSIM LANGUAGE : System Verilog (HVL) METHODOLOGY : Constrained Random Verification 2. FLOW ... - 2015 Dec 28
Seeking career in VLSI domain. Good in Verilog, Cadence, FPGA
Pune, MH, India
... Tech Final Year Team Size: Individual Contribution Role Played: Design, Test-bench and Implementation Skills Used: Verilog, Questasim, Matlab, Xilinxs ISE, RS-232 This work consist of design of digital filters and QRS complex detector in Xilinx’s ... - 2015 Dec 08
... Tech Final Year Team Size: Individual Contribution Role Played: Design, Test-bench and Implementation Skills Used: Verilog, Questasim, Matlab, Xilinxs ISE, RS-232 This work consist of design of digital filters and QRS complex detector in Xilinx’s ... - 2015 Dec 08