verilog,system verilog,universal verification methodology

Neelam S.Gathibandhe

M.Tech - VLSI Design (Autonomous Y.C.C.E), B.E - Electronics

(B.D.C.O.E)

E-mail : acebss@r.postjobfree.com,

acebss@r.postjobfree.com

Mobile : +91 - 086********, +91 - 090********, +91 - 080********

Address : Plot No. K13, Himalayavishva, Nagpur Road, Wardha -442001.

OBJECTIVE

To secure a challenging position in an esteemed organization in order

to contribute my hard work

EDUCATION PROFILE

Qualificatio Institution Board/ Year of Aggregate/

n University passing Percentage

M .Tech in Autonomous Affiliated

VLSI Design Institute, to Nagpur 2013 69.20%

Y.C.C.E, Nagpur University

B.E in Bapurao Deshmuk

Electronics College of Engg. Nagpur 2010 69.75%

Engineering, University

Sewagram(Gandhi

City)

Jankidevi Bajaj Maharashtra

H.S.C College of State Board 2006 68.00%

Science, Wardha

Agragami High Maharashtra

S.S.C School, Wardha State Board 2004 73.86%

SOFTWARE SKILLSET

HDL and HVL Verilog, System Verilog

Methodology Universal Verification Methodology(UVM)

ASIC Design XILINX and Questasim Software tools

Tools

Platform Verification of Design on Linux Environment

Platform Router, SPI (Serial Peripheral Interface)

CURRENT ACTIVITIES

Currently pursuing a Certification course in Design and Verification

Methodology at Maven Silicon Softech Pvt Ltd, Bangalore and underwent

hands-on training in Verilog, System Verilog and UVM modules.

Currently working on a protocol (SPI-project) using Verification

Environment (UVM).

1] SPI Master CORE Verification (Industrial Project - Currently

Working on) (Majore Project)

HVL : System Verilog TB Methodology : UVM EDA

TOOLS USED : QuestaSim

DESCRIPTION: Synchronous serial interface are widely used to provide

economical board level interface between different devices such as

microcontrollers, ADC's and DAC's. SPI is one of the standard for a

synchronous serial bus. SPI Master Core is compatible and acts as a

master for the slave. At the host side, the SPI core acts like a

WISHBONE compliant slave device. The SPI IP core provides serial

communication capabilities with external device of variable length of

transfer word. This core can be configured to connect with 32 slaves.

RESPONSIBILITES:

Architect the class based Verification Environment using SV and UVM.

Work on various test cases to verify RTL module using System Verilog

Work on the Functional Coverage for Verification Signoff.

Generate functional and code coverage for the RTL verification

sign-off

2] Design and Verification of ROUTER 1x3 (Mini Project)

HDL : Verilog HDL HVL : System Verilog

TB Methodology : UVM

EDA TOOLS USED : Xilinx ISE & QuestaSim

DESCRIPTION: Router is a device that forwards data packets between

computer networks. It is an OSI layer 3 routing device. Based on the

predefined protocol, it drives incoming packets to any one among the

three output channels based on the address field contained in the

packet header. The router accepts data packets on a single 8-bit port

and routes them to one of the three output channels, channel0,

channel1 and channel2.

RESPONSIBILITES:

Implement the RTL using Verilog HDL.

Architected the class based verification environment using SV and

UVM.

Developed various test cases and verify RTL using SystemVerilog

Generate Functional Coverage and Code coverage for Verification

Signoff.

Synthesize the design

Academic PROJECTS

1] Design of Low Power Parallel FIR Digital Filter using Floating

Point MULTILPIER

(Final year project) Duration 2012-2013

The FIR Filter is used as a fundamental processing element in any

Digital Signal Processing System.

Project describe the technique of Algorithmic Strength reduction which

leads to reduction in hardware complexity by exploiting substructure

sharing

Transformation is basically implemented for the reduction in silicon

area or power consumption of VLSI design.

In many design situation the overhead hardware incurred by parallel

processing cannot be tolerated due to design area limitation.Therefore

it is beneficial to realize parallel FIR Filtering structure that

consume less area than the traditional one.

Sub modules used are ETA (Error Tolerant Adder), Modified XOR Gate,

Ripple Carry Adder,Floating Point Multiplier.

Sub-modules have been written in Verilog HDL and they synthesized and

simulated using the Xilinx ISE

2] PIC Based Printer Interfacing with SD Card (Final Year Project)

Duration 2009-2010

Project was to show how Dot Matrix Printers could be controlled under

PIC controller 18F4550.

The simplest function that can be performed on a printer is that of

printer text by taking advantage of the printer's own character

generators.The operation is to output each text character as its ASCII

value(the Data),and pulse the printer's Strobe line down and then up.

Project demonstrates the printing of text under PIC controller.

Advantage of project is that it reduces time of printing and hence

reduces cost of printing per page,reduces power consumption,user

friendly,portable.

academic achievements

Paper Paper published in International journal IJETAE (ISSN

published 2250-2459) (March 2013) Topic: "Design of low power

parallel FIR Digital Filter using Floating Point

MULTILPIER"

Dance First prize, Group Dance competition in Youth Festival

organized by Agnihotri College of Engg.,2013

First prize, Solo Dance Competition, Wardha Kala Mahotsav

organized by Wardha District,2013

First prize,Solo Dance competition at State level event

organized by Chandrapur District, 2009

First Prize in Group Folk Dance Competition conducted at

Agragami High School in 2003

First Prize in Group Dance Competition at Vidarbha level

event organized by Chandrapur District, 2010

Fine Art First position in Poster making Competition, event

organized by Electronics Engineering Students Association

at B.D College of Engineering 2007-08

Won 2nd Prize in Clay Modeling Competition, Organized at

Agragami High School in 2003

Won 2nd Prize in drawing competition, Organized at Agragami

High School, in year 2002

2nd rank in On the spot Painting Competition Organized by

Indian Dental Association and Colgate Palmolive (India)

Limited, 2003

Won 1st prize in Rangoli Competition in 2002 and 2nd prize

for consecutive two years 2003 and 2004,organised by

Agragami High School

Awarded certificate for securing B-Grade in Intermediate

Grade Drawing Examination by Government of Maharashtra in

2002

Awarded certificate for securing B-Grade for Elementary

Grade Drawing Examination by Government of Maharashtra in

2001

1st prize in Rangoli Competition 2005 organised by J.B

College of Science

Won 2nd Prize in DEAR drawing competition, organized at

Agragami High School in 1999

Other Secured 2nd position in Essay Competition organized at

Agragami High School, in year 2003

Participat Presented paper in International Conference on Global

ion Trends in Engineering and Management organized by J.D

College of Engineering, 2013

Participated in Dance Event, National Level Inter College

Youth Competition SPARSH, organized by Datta Meghe

Institute of Engineering, Technology & Research, in year

2013

Participated in Margkraman and Robokesari Competition in

13th ISTE State Convention of Maharashtra & Goa and

National Level Techfest,2010

Participated in Carrom & E-Mania Competition, event

organized by Electronics Engineering Students Association

at B.D College of Engineering 2007-08

Participated in Tesla Competition, event organized by Wheel

Spin "A National Level TECH-FEST" 2009

ADDITIONAL INFORMATION

Hobby Playing Guitar, Drawing & Painting, Swimming, Dance

Language English, Hindi & Marathi.

known

I hereby declare that the particulars furnished above are true to the best

of my knowledge.

Place : Wardha

Current place : Bangalore

Date :16/05/.2014

Neelam S.Gathibandhe

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