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Project Data

Location:
Pune, Maharashtra, India
Posted:
December 28, 2015

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Resume:

POONAM NALAWADE

Email ID:acsxg0@r.postjobfree.com Mobile:+919*********

Objective

Looking for opportunities in VLSI industry where I can utilize my skills and knowledge for the development of organization as well as self-development.

Educational qualification

Class/Course

Name of Institute

Board/University

Year of Passing

Marks%

MS

( VLSI -CAD)

Manipal Centre for Information Science

Manipal University,

Manipal, Karanataka

2013

CGPA

8.13/10

BE

(ELECTRONICS)

K.B.P. College ENGG. Satara

Shivaji University,

Kolhapur, Maharashtra

2009

63.63

12TH

Y.C.I.S,Satara

Kolhapur Board,

Maharashtra

2005

71.67

10TH

Maharaja Sayajirao

Vidyalaya, Satara

Kolhapur Board,

Maharashtra

2003

86.53

Projects

1. TLP FORMATION OF PCI -EXPRESS

Project work involved design of packet formation of transaction layer. The test cases applied as inputs to the DUT through the driver. The processed data and signals received by the monitor and sent to scoreboard module for comparison.

Implemented RTL module in Verilog & verified using System Verilog.

Designed the class based verification environment using System Verilog.

TOOLS : Cadence NCSIM

LANGUAGE : System Verilog (HVL)

METHODOLOGY : Constrained Random Verification

2. FLOW CONTROL MECHANISM OF PCI-EXPRESS

Transaction layer is the first layer of the protocol, which interacts with Backbone/core logic. The transmitter layer ensures that it does not transmit a packet over the link to a receiver device unless the receiver device has buffer space to place the packet. The process of enforcing this policy referred as “credit based flow control”.

Project work involved design of flow control mechanism (transmitter side).

RTL coding has done in Verilog HDL language.

Implemented test benches in Verilog to apply stimulus.

TOOLS : Active HDL 7.2SE

PROGRAMING LANGUAGE : Verilog HDL

3. DESIGNING OF GATES (CELL CHARACTERIZATION)

A new implementation of high-performance gates presented. The proposed circuits have a simple structure. An optimization NOR/OR were developed using H-spice, Magic using different model files based on iterative transistor sizing.

TOOLS : HSPICE, MAGIC

4. DATA LINK LAYER OF PCI EXPRESS

Project work involved design and validation of PCI Express data link layer.

Project Intention was to understand specification of data link layer.

Verilog language has used for RTL coding.

Test bench in Verilog to validate the design.

TOOLS : Active HDL 7.2SE

LANGUAGE : Verilog HDL

Seminars

Presented a project seminar on “DATA LINK LAYER OF PCI EXPRESS”

Technical Skills

Operating System : LINUX, WINDOWS

Languages : C, Verilog HDL, System Verilog

Tools : SPICE, VCS, Active HDL, Cadence- NCsim

Internet Applications : Basic Shell scripting

Personal profile

Date of Birth : 10-06-1988

Languages Known : English, Hindi and Marathi

Hobbies : Reading

Address : At Panmalewadi, Post Varye, Tal-Dist Satara 415015

Co-curricular Activities

Got certificate of ‘Maharashtra Talent Search’

Participated national level project competition.

Participated actively in ‘QUEST COMPETITON-09’ as a volunteer

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Pune

Date : 28-12-2015

POONAM MURLIDHAR NALAWADE



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