MANIKANDAN. C

No: */**, Shyamala street, Email: ac4ga4@r.postjobfree.com

CLRI Nagar, Mobile: +91-944*******

Neelankarai, Chennai - 600115,

Tamil Nadu, India.

Professional Experience Summary

14+ Years of experience in Embedded Hardware design for telecom system and Networking boards. Professional expertise in developing Complex High speed digital design, Multilayer and Chip characterization boards. Designed boards for latest high speed technologies like PCI Express Gen2.0, Serial Rapid IO, SFI+, Gigabit Ethernet (10G and 1G), USB 2.0, SAS/SATA, MIPI, SIM, SD, DDR, DDR2, LPDDR2 and DDR3. Worked on multi-core processors such as iMX-536, BF-561, Intel Baseband controller XMM2210, and high speed Ethernet controllers such as Intel 82599, I350 and Broadcom Single and QPHYs . Also worked on Xilinx and Altera FPGA’s and CPLD’s based designs, Power management, Signal Integrity and Multilayer board stack-up design.

Current employment:

Senior Project Lead, NEC (Dec 2014 – till date)

Technical Expertise

Experience in Design of telecom systems from specification to design, development and integration

Experience in Baseband Reference Design

Experience in Complete Product / Project development cycle

Experience in providing System architecture solution from Top level product requirements

Experience in CPE, Base station and Backplane based designs

Experience in Design Reuse and hierarchical designs

Experience in Signal integrity, timing analysis and Design validation

Experience in Board bring-up and Evaluation testing

Proven ability to drive a project in which Software, PCB, Mechanical and thermal team are working across multiple locations

Experience in Driver implementation and test code development.

Proven approach to deliver first-time working design.

Product certification / Compliance (EMI / EMC compliance and safety testing)

Experience in doing design review and providing value added feedbacks

Experience in drafting Project Proposals and presentations

Team Leadership

Design Skills

Processor : iMX-536, Black-fin (multi-core), XMM2210 and ADSP

Protocols : PCIe, Ethernet, SRIO, USB and RS422

Tools Expertise

Schematics : ORCAD, Concept HDL

Layout : Allegro PCB and PADS

Signal Integrity : Hyper lynx and Allegro SI

Timing analysis : Timing Diagrammer

Debugging Tools : Visual DSP, AVR Studio, Flash Tool and Phone Tool

FPGA/CPLD Tools : Xilinx and Altera Model sim

Testing equipments : Tektronix’s DSO, Agilent’s Infinium, Protocol analyzers,

Logical analyzers, Spectrum analyzers, Smart bits

Ethernet tester and Sunrise Telecom’s10G Ethernet tester

Education

Bachelor of Engineering, Electronics and Communication from Anna University

Diploma in Electronics and Communication Engineering

Projects Summary

1.Optical and Electrical Gigabit Ethernet Interface Card (4xGbE):

Description: GbE4x-AV is the add-on module of Next Generation iPASLOLINK Series is used to provide 4 – SFP ports and Electrical potrs with each 1Gigabit interface. Designed the board based on Xilinx Artix 7 series and Broadcom QPHY devices. The key interfaces include SGMII, MDI, 1000 BASE X, FLASH and A2Y. This card will support 1588 PTP TC and SyncE.

Responsibilities

Project planning, execution and tracking

Interaction with customer for project schedule and deliverables

To draft System Requirement Specification

To draft Detailed design specifications

Hardware Design & Development of GbE4x-AV Board

To review and approve circuit Design and component selection

Schematics Design, PCB Placement & Routing Review

Review of SI Pre and Post Layout Analysis Report

Coordination with Thermal and Mechanical team

Board bring up and testing of prototypes

Lead the team of highly energetic engineers

Role : Project Lead, Team Size: 5, Project Duration: 9 Months

2.10Gbps Gigabit Ethernet Interface Card (XGbE):

Description: XGbE-MV is the add-on module of Next Generation iPASLOLINK Series is used to provide 2 – SFP ports with each 10Gbps interface. Designed the board based on Xilinx Artix 7 series and Broadcom PHY. The key interfaces include 10GBASE-KR, XAUI, SFI and A2Y.

Responsibilities

Project planning, execution and tracking

Interaction with customer for project schedule and deliverables

To draft System Requirement Specification

To draft Detailed design specifications

Hardware Design & Development of GbE-AV Board

To review and approve circuit Design and component selection

Schematics Design, PCB Placement & Routing Review

Review of SI Pre and Post Layout Analysis Report

Coordination with Thermal and Mechanical team

Board bring up and testing of prototypes

Lead the team of highly energetic engineers

Role : Project Lead, Team Size: 5, Project Duration: 5 Months

3.Gigabit Ethernet Card (GbE):

Description: GbE-AV is the add-on module of Next Generation iPASLOLINK Series is used to provide 4 – SFP ports with each 1Gigabit interface. Designed the board based on Xilinx Artix 7 series. The key interfaces include SGMII, RGMII, 1000 BASE X, FLASH and A2Y.

Responsibilities

Project planning, execution and tracking

To draft Detailed design specifications

Hardware Design & Development of GbE-AV Board

To review and approve circuit Design and component selection

Schematics Design, PCB Placement & Routing Review

Hyperlynx SI Pre and Post Layout Analysis for SGMII, RGMII, 1000 BASEX, SPI and MDIO

Coordination with Thermal and Mechanical team

Documentation & report for SI simulations

Board bring up and testing of prototypes

Lead the team of highly energetic engineers

Documentation

Customer Support

Role : Project Lead, Team Size: 5, Project Duration: 11 Months

4.Compact Spectrum Monitoring System(CSMS)

Description: CSMS is used to detect interfering and unauthorized RF transmissions, monitor emergency frequencies and protect large-area, high-value assets such as airports and seaports, as well as industrial and educational campuses. Designed the board based on Xilinx ZYNQ 7000 series, Dual Core ARM Cortex A9.The key interfaces include DDR3L, SD card, QSPI NOR flash, USB 2.0, GPS, Gigabit Ethernet, OCXO DAC, ADC, PCIe, SATA and HDMI.

Responsibilities

Project planning, execution and tracking

To draft Detailed design specifications

Hardware Design & Development of CSMS Board

To review and approve circuit Design and component selection

Schematics Design, PCB Placement & Routing Review

Hyperlynx SI Pre and Post Layout Analysis for DDR3L Memory, PCIe, JESD204B, Gigabit Ethernet and HDMI

Coordination with Thermal and Mechanical team

Documentation & report for SI simulations

EMI & EMC Design and Certifications

Board bring up and testing of prototypes

Lead the team of highly energetic engineers

Documentation

Customer Support

Role : Project Lead, Team Size: 6, Project Duration: 6 Months

5.Mobile SoC Evaluation board Design & Testing (Smart phone)

Description: The System Validation Board validates Intel Mobile set chip XMM™2210. XMM™2210 is an Entry phone and Ultra Low Cost platform from Intel Mobile

Communication based on the XGOLD™221 chipset. In order to meet the demands of an increasing complex market, the XMM™2210 platform is designed with a wide variety of features to enable a wide range of scalability. XGOLD™221 is a GSM/GPRS/EDGE-RX baseband controller.

Responsibilities

Project planning, execution and tracking

To draft Detailed design specifications

To review and approve circuit Design and component selection

PCB Layout review and approval

To drive software design team and to track deliverables

Board bring up and testing of prototypes

High Speed Digital Interface Compliance test

Troubleshooting of faulty boards (card specific issues)

DVT results review

Approval for Revision changes

Lead the team of highly energetic engineers

Documentation

Customer Support

Role : Project Lead, Team Size: 8, Project Duration: 14 Months

6.Solid State Drive (M.2 From Factor)

Description: The SSD Module paves the way for thin and light computing devices by introducing the latest M.2 form factor. The SSD M.2 form factor shrinks the total storage area significantly versus traditional 2.5” form factor storage devices along with the M.2 form factor. The SSD capacity is 32GB. The Solid State Drive (SSD) Controller delivers 6Gbps Serial ATA (SATA) performance with maximum flexibility, modularity, and low power-consumption. The SSD Controller is the ideal solution for rapid development of high-performance Solid State Drive systems for mobile and enterprise applications.

Responsibilities

To draft Detailed design specifications

Component selection, Design analysis and Schematics drafting

Role : Project Lead, Project Duration: 2 Months

7.Rear Transition Module for ATCA (Advanced Telecommunication Computing Architecture)

Description: The RTM provides the IO connection for the Board towards the back of the system and powered by the front board. RTM is a rear transition module as defined in PICMG 3.0 Revision 3.0 Advanced TCA Base Specification. It provides several 10G/1G Ethernet and SAS interfaces accessed via RTM face plate. It also supports Hot-swappable SAS Hard disk drive.

Responsibilities

Project planning, execution and tracking

To draft Detailed design specifications

To review and approve circuit Design and component selection

PCB Layout review and approval

S-parameter generation for Board traces using Allegro PCB SI

To co-ordinate with mechanical design team, Thermal design team and vendors

To drive software design team and to track deliverables

Board bring up and testing of prototypes

Troubleshooting of faulty boards (card specific issues)

Resolving system integration issues (when integrating RTM with ATCA blades)

DVT results review

Approval for Revision changes

Lead the team of highly energetic engineers

EMI & EMC and Environmental testing and certificate

Documentation

Role : Senior Hardware Design, Team Size: 4, Project Duration: 10 Months

8.Fish River Island Series II I/O Carrier Card

Description: The COM Express processor card will be a 55mm x 84mm circuit board that supports the Intel® E6xx Atom™ processor and EG20 PCH. This card will serve as a “daughter card” for the Fish River Island Series II and optionally for the Pearl River Island configurations.

Responsibilities

Design and implementation of complete Hardware

Component selection, Design analysis and Schematics drafting

PCB layout design review and approval

Board bring up and testing

Performance testing System integration and support

Documentation

Role : Senior Hardware Design, Team Size: 2, Project Duration: 3 Months

9.CPE for BBcorDECT NG (Broadband corDECT Next Generation, 3G)

Description: The BBcorDECT Customer Premises Equipment supporting voice and up to

2Mbps Data connectivity in fixed WiLL system. The design supports wideband channel and adaptive modulation (up to 64-QAM).

Responsibilities

Developed System architecture with the help of Industry experts

Design and implementation of complete Hardware required for CPE

Design review and optimization

Designed and Simulated control Logic for FPGA in Verilog

Driver and test code development

Complete support for Software application development

Signal integrity analysis for local bus interfaces

Design Reuse plan and execution

Design validation plan and execution

Air Interface Module designed with ETSI DECT physical layer specifications as per ETS-300-175-2

System Level Testing

Baseband and RF Module integration Testing for Functionality verification

RF Interface Testing

RF Control programming

Lead the team of highly energetic engineers

Technology transfer to TOT team and Production support

Customer and vendor interaction

Release management

EMI & EMC testing and certificate

Documentation

Role: Project Lead, Team Size: 4, Project Duration: 18 Months

10. FRS (Fixed Remote Station), 2.5G

Description: DECT Subscriber Terminal provides voice and 512kbps Data connectivity in fixed WiLL Technology with MLM (Multi Level Modulation) support.

Responsibilities

Product management

Design and implementation of complete hardware required for FRS

Technical guidance to Design, Development and testing teams

Control Logic Design, Multi Level Modulation selection and Simulation of CPLD

Timing analysis and interfacing design

Driver and test code development

Baseband and RF Module integration Testing for Functionality verification

RF Interface Testing

RF Control Programming

Customer and vendor interaction

EMI & EMC testing and certificate

Documentation

Role : Team Lead, Team Size: 3, Project Duration: 26 Months

11.DTM (DECT Transceiver Module), 2G

Description: DTM is outdoor unit of subscriber terminal equipment in split architecture. It consists of ADI Processor, Base band processor and RF section with integrated antenna. Direct Connection to the Ground unit is through RS422 Interface.

Responsibilities

Designed and implemented complete hardware required for different DTM-5xx versions

Processor (DSP) selection, Software tools and development support from vendor.

Designed and Simulated for RS422 Interface

Involved Layout design and Review

Developed Test code and Test cases

Involved in Testing and Qualification of the Prototype Card

Functional Testing of the integrated RF modules

Complete support for Software application development

Technology transfer to ToT (Technology of Transfer) team and Production support

vendor interaction

EMI & EMC testing

Documentation

Role : Team Lead, Team Size: 3, Project Duration: 28 Months

12.SBIIC (Salamander base band reference design development)

Description: The reference design for SBI (DECT Burst mode controller in ASIC) was

Implemented on a XILINX Spartan3E FPGA. The design involves Black-fin DSP,

Ethernet interface and USB interface for it to fully function as a subscriber terminal.

Responsibilities

Designed and implemented complete hardware required for Baseband ASIC device SBIIC Reference Board

Designed and Simulated for RS422 Interface

Developed the testing methodologies for analyzing RS422 performance

Involved in porting the RS422 interface logic in SOC (System on Chip)

Timing analysis and interfacing design

Involved Layout design and Review

Involved in Testing and Qualification of the Prototype ASIC ICs

Complete Support for ToT (Technology of Transfer) and Software development

Documentation

Role : Senior Hardware Design, Team Size: 3, Project Duration: 12 Months

13.Salamander Base band interface chip design and development

Description: The Salamander Base band Interface (SBI) chip, has all the necessary DECT base band interface functions like TDMA counters, programmable transmit base band, DECT encryption support, RF module control interface, RS422 based high speed proprietary network interface, configurable sync ports,

On chip: Oscillator, voltage reference, transmit DAC, receive and RSSI ADC, watchdog, POR, RS422 transceiver. SBI supports multi-level GFSK and 3G DECT base band interface.

14.RS422 based proprietary Network Interface

Description: A RS422 based proprietary link with a capacity of 1.536Mbps was designed and implemented with a XILINX CPLD. The SBI RS422 module consists of a master mode RS422 controller and off-chip RS422 transceiver. The RS422 module transmits data based on the network timing. The receive section of RS422 extracts the timing from the received data using a DPLL. Scrambling is done on the data “packet” in this link using Manchester encoding to avoid along runs of 1’s and 0’s, and hence making the marker detection easier.

Role : Hardware design and RS422 Logic Implementation, Team Size: 2, Project Duration: 5 Months

15.MLTG With 2-wire testing (Multi Load Traffic Generator)

Description: This Multi Subscriber Load Test Generator (MSLTG) is used to simulate voice traffic in the existing corDECT system. It performs two-wire test in subscriber terminals. It also performs on-hook/off-hook generation, metering pulse detection, ring detection, voice-path checking, call establishment, call processing and call termination scenario controlled by a PC with USB interface. Hardware implemented with an ADSP2191 processor.

Responsibilities

Involved in Complete Schematic and Board Design

Involved testing methodologies for analyzing Two wire performance

Coordinate with Software and Validation Team for Testing.

Documentation

Role : Hardware Design, Project Duration: 14 Months

16.Development of Multi-wallset Subscriber Terminal

Description: Multi-wallset is the corDECT subscriber terminal unit that supports simultaneously four subscribers. It is significantly reduces the cost per line of the subscriber terminal.

Responsibilities

Involved in Schematic and Board Design

Involved testing and validation

Support to Engineering and Production Team

Qualification of the Prototype Card.

Involved field testing

Documentation

Role : Hardware Design, Project Duration: 18 Months

17.LCD Projector

Description: A LCD projector is a type of slide projector for displaying data on the screen. This project is aimed at building a LCD controller for project. It is useful for Business and School environments and also reduced cost enormously.

Responsibilities

Involved in Complete Hardware Design

Test code Development

CPLD Logic Implementation

Documentation

Role : Hardware Design, Project Duration: 10 Months

18.BSD (Base Station Distributor)

Description: This project is aimed at building an intermediate unit between Exchange and CBS (Compact Base Station). This mainly supports long distance communication especially in rural and urban areas using the WLL Technology.

Responsibilities

Involved in Complete Board Design

Involved testing and Development

Involved in Testing and Qualification of the Prototype Card.

Support to Engineering and Production Team

Involved EMI & EMC Testing

Documentation

Role : Hardware Design, Project Duration: 18 Months

Employment details:

Project Lead, L&T INFOTECH - (Dec 2010 – Dec 2014)

Development Engineer, Midas Communication Technologies – (Aug 2003 – Dec 2010).

Assistant Engineer, Midas Communication Technologies – (Mar 2001 – July 2003).

Senior Project Technician, IC & SR, IIT Madras – (June 2000 – Mar 2001).

Project Technician, IC & SR, IIT Madras – (Oct 1997 – June 2000).

Personal Details:

Date of Birth : 03rd Jul, 1974

Marital Status : Married

Passport Number : G8049307

Nationality : Indian

Place: Chennai, India

[Manikandan.C]

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