Seeking career in VLSI domain. Good in Verilog, Cadence, FPGA
Resume:
Maruti Vitthal Raykar
Row House No. -*, Shri Nagari Society,
Amanora Park Town, Hadapsar, Pune-411028
Mobile: +91-770*******
E-mail ID: ************@*****.***
Carrier Objective
Continuously work in technological platforms and grow as a technologist to develop and provide innovative, cost effective, high impact solutions & products for the marketplace
Academics
2015 – M.Tech (CGPA 8.30) in Microelectronics and VLSI Design from Shri G. S. Institute of Technology and Science, Indore, Madhya Pradesh.
2013 – B.E. (65.73%) in Electronics and Telecommunication from Pad. Dr. D. Y. Patil Institute of Engineering and Technology, Pune, Maharashtra.
2009- 12th (63.83%) from Maharashtra Board.
2007- 10th (73.69%) from Maharashtra Board.
Academic Projects Overview
FPGA Based ECG Signal Processing
Duration: Aug 2014 – July 2015, M. Tech Final Year
Team Size: Individual Contribution
Role Played: Design, Test-bench and Implementation
Skills Used: Verilog, Questasim, Matlab, Xilinxs ISE, RS-232
This work consist of design of digital filters and QRS complex detector in Xilinx’s Spartan 3E FPGA. This includes display of the information’s like presence of Arrhythmia, Heart Rate, Amplitude and Width of PQRST Points.
2-Car Vertical Elevator Design
Duration: May 2014 – Aug 2014
Team Size: 2
Role Played: Designer
Skills Used: Verilog, Basics of System Verilog, Questasim
This was the project of Mentor Graphics University Contest 2014. Each car would move up-down independently on same shaft (one top of above) without collision. This is designed for 20 floors
Full Adder Design
Duration: Jan 2014 – Feb 2014, M. Tech First Year
Team Size: Individual Contribution
Role Played: Designer, Simulation
Skills Used: Cadence Virtuoso and Spectre
An Adder is designed and simulated using UMC 180nm Technology. Total 28 number of transistors used.
Operational Amplifier Design
Duration: March 2014 – April 2014, M. Tech First Year
Team Size: Individual Contribution
Role Played: Designer, Simulation
Skills Used: Cadence Virtuoso and Spectre
An OP-AMP is designed and simulated using UMC 180nm Technology.
8 bit Priority based ALU Design
Duration: Feb 2014
Team Size: Individual Contribution
Role Played: Designer
Skills Used: Verilog, Questasim
This work is designed to perform various ALU Operations. 8*8 RAM Memory is also designed. 8 ALU operations where performed.
Ultrasonic Radar Detection System
Duration: Aug 2012 – May 2013, B. E. Final Year
Team Size: 3
Role Played: Team Lead Programmer and HW Testing
Skills Used: Assembly, Kill, Express PCB
To detect the moving objects occurred in the field and transmit information about object location on mobile through SMS.
Technical Skills
Programing Languages:
Verilog HDL, VHDL, Basics of System Verilog Assertions, Basics of C, Matlab, Basics of Assembly.
Tools Handled:
Cadence, Tanner, Xilinx, Modelsim, Questasim, Express PCB, MATLAB, Keil.
Certifications
Twelve days Short Term Fast Track course on Verilog and Basic System Verilog Assertions by Techlabs Hyderabad.
Five days course on Integrated Circuit Design with Mentor Graphics: From Specification to GDSII by Techlabs Pune.
Five days course on Analog and Mixed Signal System Design.
Three days Short Term course on VLSI Design by MANIT Bhopal
Co – Curricular & Extra Curricular Activities
Participated in various events like Robo Race, Quiz Competition, Brain of Indore, etc.
Arranged successfully seminars on Stress Management, Mind Control for college students.
Member of nationwide youth group known as VOICE.
Personal Information
Date of Birth : 15th Jun 1991
Gender : Male
Marital Status : Single
Languages Known : English, Hindi and Marathi
Interest’s : Cooking, Reading Spiritual Books
Fathers Name : Vitthal Sakharam Raykar
Permanent Address : A/P Hangewadi, Tq- Shrigonda, Dist-Ahmednagar,
Maharashtra, 414701
I hereby declare that all the information cited above is true to the best of my Knowledge and belief.
Place: Pune
Date: 2/12 /2015 Maruti V. Raykar
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