| Distance: | Resume alert | Resumes 141 - 150 of 727 |
Engineering Design
Vasant Nagar, Karnataka, India
... SUMMARY OF QUALIFICATIONS: Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using ... - 2019 Apr 19
... SUMMARY OF QUALIFICATIONS: Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using ... - 2019 Apr 19
Design Engineering
Vasant Nagar, Karnataka, India
... 10th cross #1/1, Mobile: +91-886******* Kothnur Post, Bengaluru-560077 LinkedIn ID ************@*****.*** Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Apr 10
... 10th cross #1/1, Mobile: +91-886******* Kothnur Post, Bengaluru-560077 LinkedIn ID ************@*****.*** Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Apr 10
Design Verification Engineer
Vasant Nagar, Karnataka, India
... on Digital Design concepts – Combinational and Sequential circuits • Extensive experience in writing RTL models using Verilog HDL • Good experience in writing Test benches using SystemVerilog and UVM • Very good knowledge in verification ... - 2019 Apr 05
... on Digital Design concepts – Combinational and Sequential circuits • Extensive experience in writing RTL models using Verilog HDL • Good experience in writing Test benches using SystemVerilog and UVM • Very good knowledge in verification ... - 2019 Apr 05
Test Cases
Vasant Nagar, Karnataka, India
... Proficient in UVM, System Verilog, Verilog and digital logic design. Hands-on experience in protocols like Protocols AXI, AHB, SPI, I2C. Hands on experience in developing Test bench environments in UVM. Good knowledge of writing Test Plan ... - 2019 Apr 04
... Proficient in UVM, System Verilog, Verilog and digital logic design. Hands-on experience in protocols like Protocols AXI, AHB, SPI, I2C. Hands on experience in developing Test bench environments in UVM. Good knowledge of writing Test Plan ... - 2019 Apr 04
Training Design
Bangalore, Karnataka, India
... Understanding knowledge in RTL coding (Verilog and VHDL) with FPGA Prototype. • Exposure to EDA Tools: Synopsis IC-Compiler. • Operating System and Programming Language: Windows, Unix, TCL, VHDL and Verilog. INTERNSHIP AND TRAINING: • Physical ... - 2019 Mar 05
... Understanding knowledge in RTL coding (Verilog and VHDL) with FPGA Prototype. • Exposure to EDA Tools: Synopsis IC-Compiler. • Operating System and Programming Language: Windows, Unix, TCL, VHDL and Verilog. INTERNSHIP AND TRAINING: • Physical ... - 2019 Mar 05
Design Training
LBS Nagar, Karnataka, 560017, India
... Ltd, Bangalore, during Aug 2018 to Feb 2019 Design Verification Training Course Outline: Design verification training includes ASIC design flow, IP & SoC verification plan & flow, Verilog, System Verilog (OOPs, Classes, randomization, interface, ... - 2019 Mar 04
... Ltd, Bangalore, during Aug 2018 to Feb 2019 Design Verification Training Course Outline: Design verification training includes ASIC design flow, IP & SoC verification plan & flow, Verilog, System Verilog (OOPs, Classes, randomization, interface, ... - 2019 Mar 04
Engineer Project
Bangalore, Karnataka, India
... Experience on Test Plan & Test bench development in UVM environment Experience in building Verification Environment from scratch using Verilog, System Verilog and methodologies like UVM. Experience in System Verilog Assertion Good understanding of ... - 2019 Feb 18
... Experience on Test Plan & Test bench development in UVM environment Experience in building Verification Environment from scratch using Verilog, System Verilog and methodologies like UVM. Experience in System Verilog Assertion Good understanding of ... - 2019 Feb 18
Engineering Technical
Bangalore, Karnataka, India
... FIELD OF INTEREST VLSI Digital Electronics Digital Signal Processing Networking SOFTWARE SKILLS AND LANGUAGES C C++ JAVA Beginner Verilog ACHIEVEMENTS Have won 2 nd prize in the event of Technical Quiz in National Level Technical Symposium conducted ... - 2018 Dec 06
... FIELD OF INTEREST VLSI Digital Electronics Digital Signal Processing Networking SOFTWARE SKILLS AND LANGUAGES C C++ JAVA Beginner Verilog ACHIEVEMENTS Have won 2 nd prize in the event of Technical Quiz in National Level Technical Symposium conducted ... - 2018 Dec 06
Engineer Design
Bangalore, Karnataka, India
... Technical Areas of Interest Physical Design Verilog PCB Design FPGA ASIC Projects undergone Mini Projects Development and Analysis of State Variable Filter: --(Matlab) Design and Implementation of 4:16 Bit Decoder: --(VIRTUOSO) Development of FSM ... - 2018 Oct 29
... Technical Areas of Interest Physical Design Verilog PCB Design FPGA ASIC Projects undergone Mini Projects Development and Analysis of State Variable Filter: --(Matlab) Design and Implementation of 4:16 Bit Decoder: --(VIRTUOSO) Development of FSM ... - 2018 Oct 29
Design Project
Bangalore, Karnataka, India
... Familiar with writing Test Benches in Verilog and System Verilog and basic knowledge on UVM methodologies. Good understanding of ASIC design flow. Hands on Experience with industry tools like Riviera Pro and Questa sim. Pursuing PCB design course ... - 2018 Oct 23
... Familiar with writing Test Benches in Verilog and System Verilog and basic knowledge on UVM methodologies. Good understanding of ASIC design flow. Hands on Experience with industry tools like Riviera Pro and Questa sim. Pursuing PCB design course ... - 2018 Oct 23