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Mukund Sojitra

Email ID:ac8iyf@r.postjobfree.com

Contact No:951-***-****

PROFESSIONAL SUMMARY

4.5 years of total industrial experience with 2.6 year of experience in ASIC Verification.

Experience on Ethernet protocol.

Good knowledge of AHB, APB & DDR protocols.

Proficient in writing test cases, simulation and debugging.

Experience on Test Plan & Test bench development in UVM environment

Experience in building Verification Environment from scratch using Verilog, System Verilog and methodologies like UVM.

Experience in System Verilog Assertion

Good understanding of VHDL, Verilog, SystemVerilog & UVM.

Good at developing the automation script using bash, Perl

Good understanding of ASIC Design Flow, Design Verification Techniques & Digital Electronics. PROFESSIONAL EXPERIENCE

Company: PerfectVIPs Verification Engineer Jul 2016 - till date PROJECT DETAIL

Project: Tool Validation Client: Synopsys August 2017 – till date Description: Simulation Acceleration(SimXL) is aimed to modify Zebu flow so, Zebu (Emulator tool of Synopsys) can support SVTB for RTL verification rather than C based test bench are used in the process at present.

This project could speed up verification process by eliminating resource and time spent on developing C based test bench for verifying RTL on Emulator. Roles&Responsibilities:

Understanding various flow like VCS to XTOR and VCS to ZEBU flow, and tools involving in the flow for apply stimulus generated in SVTB to RTL present in FPGA.

Writing SV based tests and converts them in V2VX and V2Z format to verify features supported by SimXL from time to time.

Debugging issues encountered with above and reporting to R & D.

Add those tests in nightly and report if any variation found over updated VCS build Project: Ethernet Client: Start up May 2017–August 2017 Description: The project involves verification of PCS and FEC layer of 40/100G of Ethernet. Roles & Responsibilities:

Studied 1G, 10G, 40G, 50G, 100G Ethernet.

Developed verification code for 40/100G PCS Transmitter and Receiver.

Blocks involved in PCS Transmitter are

Encoder

Scrambler

Block Distribution

Alignment Marker Insertion

Blocks involved in PCS Receiver are

2

Block Lock State Diagram

AM Lock State Diagram

Lane reorder

AM removal

Descrambler

Decoder

Created Functional coverage’s for each block mentioned above.

Wrote test plan and test case for transmitter and receiver side of 40/100G PCS Ethernet.

Wrote a callback to inject the error in Block and AM lock state diagram and Lane Reorder.

Wrote test sequences for particular test cases in 40/100G PCS.

Built the UVM environment for Transmitter and Receiver for 40/100G PCS, connected them using PMA interface and achieved desired output.

Wrote Test plan for annex 31-B (control Pause operation) and 31-D (control PFC operation). Project: System Verilog Assertion for Tool Validation Client: Synopsys Sep 2016 -May 2017 Description: The project involves validation of Tool using System Verilog Assertion. Roles & Responsibilities:

Wrote test cases using System Verilog Assertion to check all Rules to validate tool.

Developed the automation script using bash, Perl to run all test cases.

Compared the generated new report file with all Variants and Scenarios to find Bugs Project: AHB, APB & DDR Protocol Jul 2016 – Sep 2016 Description: The project involves understanding of AHB, APB & DDR protocols. Roles & Responsibilities:

Studied the AMBA specification sheet of AHB and APB.

Developed Test plan, Test cases and Test sequences for AHB, APB.

Studied the Specification sheet, architecture, state diagram and commands of DDR protocol. Company: Star Light Luminotech R&D Engineer Aug 2014 – Jul 2016 Description: It involves development of products like LED Bulb, LED Tubelight, LED Street Light, LED Panel Light etc. for different wattages with designing of LED driver and LED PCB for all LED Products.

Roles & Responsibilities:

Lead the team of LED Lighting Product Development.

Involved in design & develop LED Lighting products which include design (Thermal, Electronics)

Managed new product development projects from concept to launch.

Interacted with vendors/manufacturers to develop the non-dimmable LED drivers.

Involved in validation of products as per BIS, IES standards.

Released product documentation including BOM & specification list etc.

Evaluated and released alternate components, sources and designs for cost reduction.

TRAINING DETAIL

Did VLSI training course at Vector India Institute, Hyderabad from 15 October, 2012 to 15 March, 2013

TECHNICAL SKILLS

Protocol Knowledge: Ethernet, AHB, APB, DDR

3

HDL & HVL: VHDL, Verilog, System Verilog

FPGA: Xilinx ISE 12.3i

Programming Language: C,C++

Scripting Language: Perl

Tool: QuestSim, VCS

Methodology: UVM

Education

BE in Electronics & Communication from GTU, 2012 with 8.02 CGPA

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