Design Training

B. Urmila

E-Mail: ***************@*****.***

Mobile: +91-630*******

Summary

Undergone Design Verification training from ChipEdge Technologies Pvt. Ltd, Bangalore, during Aug 2018 to Feb 2019

Design Verification Training

Course Outline:

Design verification training includes ASIC design flow, IP & SoC verification plan & flow, Verilog, System Verilog (OOPs, Classes, randomization, interface, functional coverage, assertions), test bench architecture, UVM (TLM, components and Objects, config_db, factory, sequence item & sequences, virtual sequences, RAL), lab after topic.

Projects experience: RAM code in system Verilog

ALU Verification:

written testbench architecture and test plan

Developed testbench using Verilog

Simulated, understood the data and control flow using basic models

Language and tools: Verilog and Aldec Riviera Pro 2017.2

Sync FIFO Verification:

Written the verification plan and test plan

Testbench development using Verilog

Design and integration of BFMs in the testbench and verified FIFO

Language and tools: Verilog and Aldec Riviera Pro 2017.2

Memory controller Verification:

Developed testbench using System Verilog components, including driver, monitor, coverage collectors

Used mail-box for data movement between class-based components

Language and tools: System Verilog and Aldec Riviera Pro 2017.2

Router (1x4) Verification:

Developed all UVM testbench components from scratch, connected components for a router-1x4 DUT

Simulated the testbench with DUT

Language, methodology and tools: System Verilog, UVM and Aldec Riviera Pro 2017.2

Technical Skills

Programming Language: C, Verilog, SV, UVM,

Operating System: Windows

Software Tool: Aldec Riviera Pro 2017.2, Xilinx 14.4, ModelSim, Putty.

Microcontroller (uC) &,Microprocessor (uP): 8085, 8051, PIC (12F, 16F, 18F) Series, LPC21xx

Boards Explored: Spartan 3E. ARM7, STM32F4 Discovery, PIC Evaluation Board

Tester: Advantest Verigy 93K

Academic Qualification

M.Tech (VLES), Jawaharlal Nehru Technology University - Anthapur, with 72.6% passing year-2017

B.Tech (ECE) Jawaharlal Nehru Technology University - Anthapur with 64.59%, passing year-2015

M.P.C (12th) Intermediate Education, Andhra Pradesh, 60.1%, passing year-2011

S.S.C (10th) Secondary Education, Andhra Pradesh, 63.3% passing year-2009

Academic Projects

“ Handwritten Telugu vowels using Statistical histogram Oriented Gradients(HOG) Features And Feed forward neural network ”

Abstract:

In this proposed system, a feed forward neural network for characters and vowels recognition. The neural network can effectively recognize various characters such as Telugu vowels with higher rate of accuracy of recognition can be built using the feed forward neural network. A Feed forward (FF) and classifying algorithm is capable of reducing the number of neurons correspondingly and increasing recognition rates for the fixed number of output. In this method we are performing step by step procedure in order to recognize the vowels.pre processing on vowels, the adding salt &pepper noise, the noise reduction can be done using median filter and morphological to that vowels. The simulation result has been providing to see the performance of the recognition.

Domain: image processing

Personal Details

Father’s Name: B. Eswaraiah

Date of Birth: 21-08-1994

Linguistic Proficiency : English, Telugu

Address: HNo: 21,2nd cross,1st main,VB Layout,KR Puram

Bangalore,Karnataka:560036

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