| Distance: | Resume alert | Resumes 131 - 140 of 727 |
Physical Design Trainee
Bangalore, Karnataka, India
... Professional Traits Arduino ICC Innovus Perl Physical design VLSI C Synthesis STA Virtuoso Genus Tempus PNR verilog Python Seeking a quality environment where my knowledge can be shared and will have impact on company‘s growth, at the same time ... - 2019 Aug 08
... Professional Traits Arduino ICC Innovus Perl Physical design VLSI C Synthesis STA Virtuoso Genus Tempus PNR verilog Python Seeking a quality environment where my knowledge can be shared and will have impact on company‘s growth, at the same time ... - 2019 Aug 08
Design Power
Vasant Nagar, Karnataka, India
... Academic Details: Year Qualification Board/University Marks in % / CGPA 2019 M.Tech VIT University 8.28 2016 B.E Dr.B.A.M.U 7.3 2012 HSC MAHARASHTRA 78.33% 2010 SSC MAHARASHTRA 85.04% Technical skills: Programming Language Verilog HDL, PERL(beginner ... - 2019 Aug 08
... Academic Details: Year Qualification Board/University Marks in % / CGPA 2019 M.Tech VIT University 8.28 2016 B.E Dr.B.A.M.U 7.3 2012 HSC MAHARASHTRA 78.33% 2010 SSC MAHARASHTRA 85.04% Technical skills: Programming Language Verilog HDL, PERL(beginner ... - 2019 Aug 08
Design Project
Koramangala, Karnataka, India
... Skill Set EDA Tools : Cadence Virtuoso, Innovus, NCLaunch, encounter, Tempus and Vivado, Cadence Orcad, ICC2 Hardware Description Languages : Verilog. Software Skills : C-Programming. Platforms : Linux, Windows. Hardware Systems : NXP ARM Cortex M3 ... - 2019 Aug 07
... Skill Set EDA Tools : Cadence Virtuoso, Innovus, NCLaunch, encounter, Tempus and Vivado, Cadence Orcad, ICC2 Hardware Description Languages : Verilog. Software Skills : C-Programming. Platforms : Linux, Windows. Hardware Systems : NXP ARM Cortex M3 ... - 2019 Aug 07
Information Technology Data
Bangalore, Karnataka, India
... SKILLS Python MATLAB C programming Modelsim Verilog Multisim Code composer studio (CSS) MS-Office Tensor Flow OPERATING SYSTEM windows, Linux- Ubuntu, Fedora, Zorin POSITIONS OF RESPONSIBILITY Organized and hosted for Cultural Events As a part of ... - 2019 Jul 28
... SKILLS Python MATLAB C programming Modelsim Verilog Multisim Code composer studio (CSS) MS-Office Tensor Flow OPERATING SYSTEM windows, Linux- Ubuntu, Fedora, Zorin POSITIONS OF RESPONSIBILITY Organized and hosted for Cultural Events As a part of ... - 2019 Jul 28
Test Cases Engineering
Bangalore, Karnataka, India
... Projects Thesis Hardware Trojan detection using Deep Learning technique Tools Used Synopsys Tetra Max Languages Used Verilog, Python Based on controllability and transition probability analysis, trojan nodes are isolated using deep learning ... - 2019 Jul 28
... Projects Thesis Hardware Trojan detection using Deep Learning technique Tools Used Synopsys Tetra Max Languages Used Verilog, Python Based on controllability and transition probability analysis, trojan nodes are isolated using deep learning ... - 2019 Jul 28
Engineer Test Cases
Vasant Nagar, Karnataka, India
... Good Programming Skills in Verilog, System Verilog, UVM. Decent working knowledge on standard protocols like AXI, APB, UART. Strong understanding of Assertion Based Verification & Functional Coverage. Hands on experience in writing test cases, ... - 2019 Jul 21
... Good Programming Skills in Verilog, System Verilog, UVM. Decent working knowledge on standard protocols like AXI, APB, UART. Strong understanding of Assertion Based Verification & Functional Coverage. Hands on experience in writing test cases, ... - 2019 Jul 21
Design Engineering
Vasant Nagar, Karnataka, India
... Pincode-560083 Mobile: +91-954******* LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Jul 12
... Pincode-560083 Mobile: +91-954******* LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Jul 12
Verilog, System Verilog, UVM, SOC Verification, ASIC Verification
Vasant Nagar, Karnataka, India
... The following are the best skills which I believe are applicable to the position I have applied for HDL : Verilog HVL : System Verilog Protocols : AMBA, AHB, APB, SPI, AHB-APB Simulators : Riviera Pro, Questasim, Modelsim Verification Methodologies ... - 2019 Jul 08
... The following are the best skills which I believe are applicable to the position I have applied for HDL : Verilog HVL : System Verilog Protocols : AMBA, AHB, APB, SPI, AHB-APB Simulators : Riviera Pro, Questasim, Modelsim Verification Methodologies ... - 2019 Jul 08
Engineer Design
Karnataka, India
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
Project Software
Vasant Nagar, Karnataka, India
... Technical profile Languages : Verilog,C, C++, Java,VB.Net Operating System : Windows XP/windows7/windows10 Application package & tool : MS Office Educational Qualification Qualification School/College University Passed out year Percentage BCA RNS ... - 2019 May 28
... Technical profile Languages : Verilog,C, C++, Java,VB.Net Operating System : Windows XP/windows7/windows10 Application package & tool : MS Office Educational Qualification Qualification School/College University Passed out year Percentage BCA RNS ... - 2019 May 28