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Design Project

Location:
Bangalore, Karnataka, India
Posted:
October 23, 2018

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Resume:

RAGHUTTAM K KULKARNI

Email ID : - ac7g1j@r.postjobfree.com

Contact No : - +91-886*******

Objective:-

To obtain an entry level position that will provide a challenging environment to enhance my skills and grow along with the company.

Training on ASIC DESIGN VERIFICATION & PCB designing:- Completed design and verification course (QCDVE QSOCS certified design and verification engineering) in VLSI from QSOCS Technologies, Bengaluru. Six months training on ASIC Design flow and Verification. Familiar with writing Test Benches in Verilog and System Verilog and basic knowledge on UVM methodologies.

Good understanding of ASIC design flow.

Hands on Experience with industry tools like Riviera Pro and Questa sim. Pursuing PCB design course from Real Time Signals technologies Pvt.ltd. Experience in tool PCB designing tool ORCAD & ALLEGRO. VLSI Domain Skills

HDL : Verilog.

HVL : System Verilog.

EDA Tool : Riviera Pro, Modelsim, Questa sim, Orcad & Allegro. Domain : ASIC Design flow, Digital Design.

Knowledge : RTL Coding, FSM based design, Simulation, Synthesis. Operating System : Linux and Windows.

Extracurricular Activities:-

Published a research paper titled “Advanced intelligent security and self-defense system for human beings” in the International Journal of Science and Research (IJSR) volume 6, Issue 6, June 2017 (ID: ART20174956).

Secured first place in interschool basketball competition.

Participated in zonal clamber round of verbattle junior state level debate tournament in English in 11/08/2009.

Participated in the zonal round of Robo-Tryst-2104 organized by Robosapiens Technologies Pvt. Ltd. in association with Tryst-2014 IIT Delhi.

Secured second place at school level in S.S.L.C board examination held in April-2011.

Attended workshops on “Signals and Systems” conducted by Institution of Electronics and Telecommunication engineers, and “Recent Advances in Optical Communications and Networks” organized by TESLA ECE forum, Department of ECE,RGIT. Educational Profile:-

Degree Name of the

University

University/Board Percentage Year Of

Passing

B.E.(ECE) Rajiv Gandhi

Institute Of

Technology.

VTU. 60.83%(overall) 2017

PUC Alva’s Pre-

University

college

Moodbidri.

Karnataka State

PU Board.

83.5% 2013

S.S.L.C Amarjyothi Public

School.

Karnataka State

SSLC Board.

91.02% 2011

Academic Projects:-

Project Title: - Advanced Intelligence Security and Self-defense System for Human Beings. B.E. Final Year Project

Abstract

The system is a self-defense device layout for every individual. The main objective of this project is to provide protection and self-defense mechanism for every individual especially women and children being sexually harassed or who been under unethical attacks for the purpose of personal grudge etc. The project is implemented using ARM micro-controller LPC2148, GPS-GSM module, tilt-sensor

(MEMS-sensor), 16*2 LCD display, webcam, buzzer, emergency switch and an electric shock using a vibrating device. The system can be incorporated in wearable devices like wrist watch, spectacles, hand gloves or pendants. “The layout design can be further implemented as an integrated wearable device using MEMS technology and nanotechnology”.

Role Team member (Group of 4 members).

Software’s

used

Keil micro-vision, Flash-magic and Matlab.

Project Title: - Design Verification of Synchronous FIFO. Platform: Windows/Linux Language: Verilog HDL and System Verilog Tools: Riviera Pro. Objective: The project focuses on design and verification of Synchronous FIFO. The design of FIFO is done in Verilog behavioral modelling style and Verification of the same is done in System Verilog by generating random test-cases.

Design

• Designed RTL for operations of FIFO in Verilog HDL.

• For the designed RTL of FIFO functionality is verified. Verification

• Prepared the test plan.

• Prepared the test bench architecture.

• Created the test environment in System Verilog and verified the functionality of Designed FIFO.

Project Title: - Design Verification of Synchronous Dual-Port RAM. Platform: Windows/Linux Language: Verilog and System Verilog Tools: Riviera Pro. Objective: The project describes the design of Synchronous Dual-Port RAM and also verifies its functionality by creating the test environment in System Verilog. Verification

• Prepared the test plan.

• Prepared the test bench architecture.

• Created the test environment in System Verilog.

• Verified different test-cases.

Project Title: - Design Verification of UART

Platform: Windows/Linux Language: Verilog HDL and UVM Tools: Rivera Pro. Objective: The project focuses on design and verification of UART with WISHBONE protocol. UART is a serial communication protocol which allows the full duplex communication in serial link, it is an essential to computers and allows them to communicate with low speed peripheral devices, such as the keyboard, the mouse, modems etc.

Design

• Analyzed the specifications of UART-WISHBONE.

• Prepared micro-architecture for the same.

• Took the RTL of UART-WISHBONE and analyzed its functionality. Verification

• Prepared the test plan.

• Prepared the test bench architecture.

• Created the test environment in System Verilog.

• Methodology used UVM.

Personal Profile:-

Name : Raghuttam K Kulkarni.

Permanent Address : #4, Sarvesh Aradya house, 1st floor Kuvempu Nagar, Devasandra Main road K.R.Puram, Bengaluru-560036.

Date of Birth : 05-07-1995.

Nationality : Indian.

Hobbies : Sports, Reading Blogs, listening to music, PC and Mobile Gaming. Declaration:-

I hereby declare that the above information is true to the best of my knowledge. Date: Raghuttam K Kulkarni

Place: Bangalore



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