Test Cases

SMITKUMAR B. KORADIYA

Email : **************@*****.***

Mobile : +91-851*******

Career objective: To pursue challenging career and be a part of progressing organization which help to grow my knowledge and technical skill in the field of front-end design and verification and to sync with the technologies and industrial trends.

Summary:

6 month of IP/SOC verification and debugging experience.

Proficient in UVM, System Verilog, Verilog and digital logic design.

Hands-on experience in protocols like Protocols AXI, AHB, SPI, I2C.

Hands on experience in developing Test bench environments in UVM.

Good knowledge of writing Test Plan/Verification Plan document and Documentation.

Good Scripting knowledge in PERL.

Details of the projects:

1. Development of AXI 3.0 VIP and validation using AXI slave VIP

Understanding the specification and listing down all the features of AXI3.0

Developing VIP architecture and coding VIP components.

Test-case development targeting the features.

Validating AXI VIP using AXI slave model.

HVL: System verilog Tool: Questa sim 10.4e

2. Functional verification of universal memory controller

Analysis of the specification document and list down the features and developing test plan.

Template environment codding of test-bench architecture.

Coding TB components and integration of them.

Connecting different memories like SRAM, SDRAM, synchronous chip select, FLASH to DUT.

Developing sanity test cases and functional test cases.

Functional and code coverage.

HVL: System verilog Tool: Questa sim 10.4e

3. AHB UVC development

List down features, scenarios.

Test plan development.

Developing test bench architecture coding.

Verification closure using function coverage and code coverage as closing criteria.

HVL: UVM Tool: Questa sim 10.4e

4. Interrupt controller

Analysis of the specification document and listing down feature.

Checking the priority of interrupt vector.

Write a priority on the register.

Compare it with interrupt priority.

If interrupt in service so wait for micro controller become free.

Developed test-bench, compilation and simulation.

HDL: Verilog Tool: Questa sim 10.4e

Education qualification:

Qualification/

course

Specialization Name of the

college/institute

Year of study Grade acquired

VLSI front-end Front-end design and

verification

VLSIguru institute 2018 Completed success

fully

Bachelor of

engineering

Electronics &

communication

GEC, Bhavnagar 2015 – 2018 CGPA - 7.77

Diploma

engineering

Electronics &

communication

Darshan engg. of

diploma study

2012 – 2015 CGPA - 8.43

SSC -

Sarvodaya science

school

2011 – 2012 66.45 (PR)

Technical skill:

Protocols : I2C,SPI,APB,AHB,AXI

HDL : Verilog

HVL / Methodology : System verilog, Basic knowledge of UVM

Tools : Questa sim 10.4e, Model sim 10.4a, Gvim 8.0

Programming languages : Basic knowledge scripting Perl, C, C++

Operating system : windows, UNIX/Linux

Other projects:

VLSI projects

Dual-port RAM

FIFO

Watchdog timer

Pattern detector

Achievement:

Coordinated the electro enigma event (circuit design & PCB design) during aashlesha national tech-fest organized in our collage during-2017.

Participated in Hogwarts (technical game) aashlesha-2017, GEC Bhavnagar.

Participated in electro scribe event (make a conducting ink) in prakarsh-2015, a national level technical symposium organization as SVIT.

Personal vitae:

Date of Birth : August 01, 1996

Gender : Male

Address : Rajkot (Gujarat)

Strengths : Self-discipline, Self-confident, Co-operative and Flexible nature Languages : English, Hindi, Gujarati

Place: Bangalore (SMITKUMAR)

Academic projects

Bag security system (smart bag)

Automatic DTH antenna

Foot step energy generation

Contact this candidate