Engineer Test Cases
Resume:
Bommidala Datta Sai Akhil Mobile: 846-***-****
Email : ***********@*****.***
CAREER SUMMARY:
~2 Years’ experience as a Design Verification Engineer.
Good Programming Skills in Verilog, System Verilog, UVM.
Decent working knowledge on standard protocols like AXI, APB, UART.
Strong understanding of Assertion Based Verification & Functional Coverage.
Hands on experience in writing test cases, developing verification plan at IP level.
Have specification knowledge on PCIE.
TECHNICAL SKILLS:
Programming Languages : Verilog HDL, System Verilog, UVM.
Protocols : APB, AXI3, UART.
Scripting languages : Perl.
Tools : G-Vim, Questa-sim, Xilinx ISE.
EXPERIENCE:
Name of The Company
Designation
Experience
UST-Global
Design Verification Engineer I
June 2017- Present
PROJECT DETAILS:
Project :System Verilog Assertion Bring up for Phoenix SIW (Korean based) - SeviTech ODC . (Jan 2019-June)
Responsibility:
Writing and debugging assertions for different scenarios of IP level blocks for PHEONIX SOC.
Running testcases in regression and debugging the errors.
Project : AXI Interconnect Automation ( June 2018 – Jan 2019 )
Description: The SoC uses AXI-interconnect for single master, four slave’s configuration. The interconnect is generated from Perl-based automation using the configuration given as input with one AXI port and three AHB ports. The interconnect uses all the features like burst types, burst lengths and burst size. The interconnect uses the base address to arbitrate the transfer to the desired slave.
.Responsibilities:
Understood the automation flow of Perl script and modifications
Understood the existing 1 master 2 slave environment VIP.
Fixed the bugs in the existing Perl script.
Developed the performance monitoring for a single transaction.
Bring up and debugging of test cases for the 1 master 4 slave environment.
Bring up and debugging of C test cases for SOC corner level.
Understood the total SOC flow.
Project : Verification of UART using UVM ( Mar 2018 – June 2018) .
Description : UART is to transmit and receive the serial data with 5bit or 6bit or 7 bit or 8 bit in Loopback, full-duplex and half-duplex mode. This is wishbone compatible and it supports only FIFO mode.
Responsibilities :
Understood the specifications of UART protocol.
Developed UART by connecting AHB to WB bridge to UART.
Developed sequences for 5bit, 6bit, 7bit, 8bit, even / odd / stick priority test cases.
Running the Regressions and Debugging the issues.
Developed the code coverage and functional coverage.
Project : Verification of APB using UVM ( Nov 2017 – Mar 2018) .
Description : APB master VIP is developed to check the APB slave and the data transactions between the both using different burst types and burst lengths.
Responsibilities :
Understood the specifications of APB protocol.
Running the Regressions of all the testcases.
Developed the code coverage and functional coverage.
Project : Verification of Router 1X3 using UVM ( July 2017– Nov 2017)
Description : The router accepts data packets based on the different address of the slaves and routes them to one of three output channels. If the slave is not able to accept the data within 30 clock cycles, then the data will be sent to the source again.
Responsibilities :
Understood the specifications of Router Protocol.
Developed Single master three Slave VIP Environment.
Developed different test cases and corner cases .
Running the Regressions and Debugging the issues.
Developed the code coverage and functional coverage.
EDUCATIONAL QUALIFICATION:
COURSE
INSTITUTION
BOARD
YEAR OF PASS
AGGREGATE
B.Tech
( ECE )
Narasaraopeta engineering college.
JNTU, Kakinada.
2017
74.42
intermediate
NRI academy
State,Andhra Pradesh.
2013
80.5
10th
Kendriya Vidalaya
CBSE, Andhra Pradesh.
2011
8.0
PERSONAL DETAILS:
Date of birth : 29th December 1995.
Gender : Male.
Marital Status : Single.
Languages known : English,hindi,Telugu.
DECLARATION:
I hereby declare that the details stated above are true and correct to the best of my knowledge and belief.
(Sai Akhil )
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