Engineer Design

XIQIAN WANG

*** **** **** **. ***** Clara, CA ***54

+1-323-***-**** ********@***.***

SUMMERY

VLSI engineer, focusing on ASIC design and veri cation, seeking full-time job Auguest 2019. EDUCATION

University of Southern California (USC), Los Angeles, CA August 2017 - August 2019 M.S. of Electrical Engineering

Courses: EE457 Computer Systems Organization, EE477 MOS VLSI Circuit Design, EE552 Asyn- chronous VLSI Design, EE577A & B VLSI System Design, EE599 Software Design and Optimization for Hareware Engineer, EE580 System Veri cation

Beijing Information Science & Technology University (BISTU), Beijing, China July 2016 B.E. of electronic information engineering

TECHNICAL SKILLS

Computer Languages C/C++, Python, Verilog, SystemVerilog, Shell/TCL Script Software & Tools UVM, Cadence Virtuoso, Modelsim, MATLAB, PT, DC, Linux,LaTeX RESEARCH EXPERIENCE

Many-Core System Mapping - A Wavelet Clustering and Ant Swarm Optimization Based Framework-Paper pending Dec.2018 - August 2019

Combining machine learning (wavelet clustering) with collective intelligence algorithm to build a map- ping framework for Network-on-Chip (NoC).

Experiment results on a 64-core NoC show considerable improvements’ compared to existing approaches.

Improves energy e ciency by 19%,performance by 65.86%. Using Generating Model for Hardware Veri cation Jan.2019 - May.2019

Using Generative Adversarial Network (GAN) to verify hardware design and nd more fail tests using less tests( nd 18 failed examples in 7257 tests, while traditional random test nd 6 in 10000).

Veri ed the GAN works for model checking, only tested for several random designed models, now trying to verify real-world models.

PROJECTS

Gold Network-On-Chip Nov - August 2018

Modelsim, DC,PT

RTL design of Network-on-Chip (NoC) with ring topology that data can go either clockwise or conter- clockwise.

Synthesis RTL code to gate-level netlist by Design Compiler, then check timing issue by Prime Time. Implementing an SAT Solver June - Auguest.2018

Python, minisat

Design an SAT Solver that can determine a Boolean expression is evaluated to be satis able.

Using hill climging to make the SAT slover works faster.

Comparing result with minisat to make sure the slover works correctly. Asynchronous Network-On-Chip March - May.2018

Modelsim, UVM

Using system Verilog to build an asynchronous NoC with cluster tree topology, hamming code correction.

Using UVM to verify the design and x bus.

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