To secure an entry level Electrical Engineering position in a dynamic semiconductor organization that offers a positive atmosphere to learn and to use my skills for the benefit of the company.
MS: Electrical Engineering (Dec 2018) San Jose State University (CA)
B.Tech: Electrical and Electronics Engineering (2012) Uttar Pradesh Technical University (India)
Digital System Design and Synthesis, ASIC CMOS Design, High Speed CMOS Circuits, SoC Design and Verification with System Verilog, Advance Computer Architecture, Design of CMOS Digital Integrated Circuits.
Languages and/or HDL - Verilog, System Verilog, Perl, C++
EDA Tools - Synopsys VCS, Cadence Incisive, NCSim, Virtuoso, Spectre, Hspice, Xilinx ISE, ModelSim
Operating Systems - Linux, Windows, macOS
Familiarities – ASIC/FPGA design Simulation and Synthesis, Static Timing Analysis, CDC, Functional Verification and Coverage, Assertion, LINT, IC layout, Bus protocols: AMBA, AXI, AHB, APB
Network On Chip Interface (Teamwork) – Synopsys VCS, System Verilog, Linux (Spring 2018) Designed NOC bus that communicates to 16 distinct timers. Bus exchanges read and write data frames in packets. Synthesized and performed timing analysis and optimized the design for low latency.
Pipelined 5 stage Floating point adder & Multiplier (Individual)- ModelSim, Verilog HDL (Fall 2018)
Implemented a 32-bit Binary floating-point Adder & Multiplier with the IEEE 754 standard using shifting, normalizing, and rounding process.
Look Back Compressor (Teamwork)- Synopsys VCS, Linux, Verilog HDL (Fall 2017) Designed a synthesizable RLE algorithm creating state machine to retrieve the data which is already been read and stored in the memory. The design doesn't have to write the data which is already been stored to save time space and the memory of the module. The operating frequency was 300 MHz.
8:3 Priority Encoder (Individual)- UNIX, Cadence Virtuoso, IC Layout (Spring 2018) Designed 74LS148 gate level 8:3 Priority encoder in different PVT conditions and typical corner cases along with testing each case in Spectre to determine which model provides the least glitch and better performance.
Conditional Sum Adder & Subtractor (Individual)- Synopsys VCS, Linux, Verilog HDL (Spring 2017) Built a 64-bit conditional sum adder using different sets of MUXs and adders which helps the design functionality faster than the other adder in terms of speed. Pre-Synthesis of the design and netlist generated.
IT Recruiter, Exertia Consulting 05/2016 to 11/2016 Responsible for Talent Acquisition, End to End Recruitment process, Screening and sourcing of candidates.
VLSI Industrial design and verification training, Sandeepani - CoreEl Technologies 03/2015 to 07/2015 Trained on courses included concepts of Digital Design, Verilog HDL, System Verilog, and functional verification.
Electrical Maintenance Engineer, N F Forging Pvt Ltd 03/2014 to 03/2015 Supervisor and Maintenance in-charge at Steel Foundry division, Molding line and Electrical Sub Station.
Electrical Maintenance Engineer, Texmaco Rail and Engineering Pvt Ltd 09/2012 to 02/2014 Supervisor of High-Pressure Molding Line and operation of the Semi-Auto plant using PLC and SCADA.