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Software Engineer Electrical Engineering

San Jose, California, United States
September 21, 2019

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Chung-Wen (Albert) Tsao

San Jose, CA ***** 408-***-****


In-depth knowledge of algorithms and data structures for combinatorial optimization, statistics, data analysis, graph and game theory.

Experienced software engineer and CAD tool supporter for complex large-scale software engineering projects: critical problem analysis, technical specification, prototyping, infrastructure planning, implementation, unit and flow test scripts, and documentation.

USA Computing Olympiad of algorithmic programming skills, Gold Division.

Strong passion about STEM technology education and distance learning.


Java, C++, C, HTML/CSS/JavaScript, PHP/MySQL/, Tcl, Cadence Place & Route tool, Linux/UNIX/Window, Python/NumPy/Pandas data wrangling/summarization/visualization


San Jose State University, 2017-now

California State University, East Bay, 2017-now

Lecturer, C++ programming, Introduction to Computer Science II, Operating System, Computer Architecture, Automata and Computing Theory

Cogswell College, San Jose, 2017-now

Adjunct Professor, Linux, Advanced C++, Computer Organization and Architecture, Data Structures and algorithms, Python Programming

Chabot College, Hayward, 2017-now

Adjunct Professor, Linux, Python Programming, Computer Literacy

San Jose City College, 2016-now

Adjunct Professor, C++, Python Programming, HTML/CSS/JavaScript/PHP/MySQL

Silicon Valley University, 2016-2017

Adjunct Professor, Data Structures and Algorithm, Operating System

Springlight Education Institute/W3 Coding School, 2014-2015

Instructor, problem analysis, algorithm design, debugging and programming skills in JAVA/C++/C/JavsScript/Tcl/Python for programming contests

Instructor, USA Computing Olympiad of algorithmic programming skills.

Online Education and Distance Learning

Cadence Design Systems, 2002 – 2013


Invented two-stage Clock Tree Synthesis (CTS) to effectively control clock skews and minimize buffering cost

Revamped the CTS algorithm to consider clock gate timing, MMMC (multi-mode & multi-corner), MV (Multi-Voltage), On-Chip Variation, high-layer and wire width assignments

Improved the effectiveness of useful skew under MMMC (Encounter CCOPT)

Improved buffering algorithms for signal nets (Encounter GigaOpt)

Researched VLSI CAD algorithms, computational geometry, combinatorial Optimization, graph and game theory, computer network modeling and analysis, performance-driven routing and buffering topology.


United States Patent # 7,051,310, May 23, 2006

"Two-Stage Clock Tree Synthesis With Buffer Distribution Balancing"

C Code for Bounded-Skew Clock Routing in VLSI, UCLA Case#. LA 97-088-01

R&D Special Achievement Award, Cadence Design Systems, Inc., 1998


Computer Science Major, University of California, Los Angeles, Ph.D. in Computer Science.

Electrical Engineering Major, National Taiwan University, Taipei.

B.S. in Electrical Engineering.

PUBLICATIONS: 7 conference papers (one best paper candidate) and 5 journal papers

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