STANLEY MATHEW

*** ******* **** **, *** Jose, California-95131

+1-352-***-****

ac96y3@r.postjobfree.com

WORK EXPERIENCE

Mentor Graphics Corporation-A Siemens business

Applications Engineer- Physical Verification 20th July 2017-Present

§ Working closely with customers to develop and implement physical verification flows (DRC, LVS, Parasitic extraction, ESD, DFM) and methodologies at mature and advanced nodes(16nm,7nm,5nm)

§ Provide onsite support to debug issues encountered by the customers with their signoff PV runs there by eliminating critical bottlenecks during tape-outs.

§ Coordinate with design engineering on various issues targeting product reliability, working with marketing and product managers to define new products and provide insight from the field back to these groups.

§ Awarded Calibre Rookie of the year FY2018 for critical contributions made in increasing Calibre presence with new and existing customers

Technical Marketing Engineer- Physical Verification 21st April, 2017- 19th July, 2017

§ Led a successful Calibre parasitic extraction tool qualification for a leading foundry in the Bay area.

§ The qualification was the first process transition from Calibre xRC to Calibre xACT Corporate Application Engineer- Support 20th June 2016-20th April 2017

§ Delivering solutions by debugging customer issues with Calibre tools like Calibre nmDRC, Calibre nmLVS, Calibre PEX, Calibre xACT, Calibre PERC and Smartfill

§ Review and publish knowledge-based articles to highlight the benefits of a particular tool usage.

§ Help customers run software across multi-machine/multi-CPU grid applications EDUCATION

§ M.S. Electrical and Computer Engineering - University of Florida, Gainesville, FL, USA May, 2016 Relevant courses: Bipolar Analog IC design, Advanced VLSI, RF Circuits and Systems, Wireless communication, Reconfigurable Computing, Mixed Signal IC Test, RF Electronics, Noise in linear systems

§ B.E. Electronics and Telecommunication Engineering - University of Mumbai, India May, 2014 Relevant courses: Analog and Digital IC design, Discrete Time Signal Processing, Electronic Devices and circuits, Advance Microwave Engineering, Mobile Communication systems, Digital Logic Design, Microprocessors and Microcontrollers SKILLS

§ Tools: Calibre PV tools, Cadence Virtuoso, Xilinx ISE, Vivado, LTSpice, Advance Design System (ADS), ModelSim.

§ Languages: TCL, VHDL, C, C++, JAVA, HTML

§ Technical Competencies: Physical verification flow, ASIC Design Flow, FPGA Design Flow, Timing Analysis, Multiple clock domain design, RF system architecture design, RTL level design and synthesis, Test Bench Generation. PROJECT EXPERIENCE

University of Florida, Gainesville

1D Time Domain Convolution using VHDL (Zynq-7000 All programmable SoC) Course: Reconfigurable Computing

§ Designed DRAM DMA interface with use of handshake synchronization and FIFO to consider metastability of signals while crossing clock domains.

§ Designed convolution pipeline with smart buffers for providing inputs and implemented saturation on pipeline output. MIPS (Microprocessor without Interlocked Pipeline Stages) Course: Advanced VLSI

§ Designed low power design with and without clock gating of MIPS-32-bit architecture and compared them for switching power, area, power dissipation, and timing parameters.

§ An improvement of 23.6% was achieved in switching power with the use of clock gating in pipelined architecture. 4x1 SRAM using a 6T cell Course: VLSI

§ Designed and implemented a 4x1 6T SRAM cell, with the smallest area as the objective.

§ The SRAM area was measured to be 419.904um2 including the entire SRAM core and peripheral circuits. The read and write access times were 0.3ns and 0.9ns.

§ Successfully performed DRC and LVS and did stability analysis for the same. Earth-Moon Wireless Link (RF system level project) Course: Radio Frequency Circuits and Systems

§ Achieved a data rate of 1 GB/s earth moon wireless link with BER of 1x10-5 using Quadrature Phase Shift Keying (QPSK) modulation scheme and heterodyne architecture.

§ Simulation and validation of the design was done using Advance Design System Software (ADS).

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