| Resume alert | Resumes 61 - 70 of 139 |
Information Security Engineering
San Jose, CA
... analysis (STA) Altered codes, ran different test cases to study variations in timing and skews to isolate False paths and ways to overcome it 6X6 Booth Multiplier March 2017 Implemented a booth multiplier which generates output with 60% more speed. ... - 2017 Jun 05
... analysis (STA) Altered codes, ran different test cases to study variations in timing and skews to isolate False paths and ways to overcome it 6X6 Booth Multiplier March 2017 Implemented a booth multiplier which generates output with 60% more speed. ... - 2017 Jun 05
Design Engineer State University
San Jose, CA
... Primetime Static timing analysis(STA). * Designed 40 64 15 ports Register File (Montalvo 3GHz). Architected and developed 6 Writes and 9 Reads with 2 Shadows high performance register file. Read access time 200ps in 65nm. LEC, timing, EMIR, SIGEM, ... - 2017 May 31
... Primetime Static timing analysis(STA). * Designed 40 64 15 ports Register File (Montalvo 3GHz). Architected and developed 6 Writes and 9 Reads with 2 Shadows high performance register file. Read access time 200ps in 65nm. LEC, timing, EMIR, SIGEM, ... - 2017 May 31
Hardware Engineer
San Jose, CA
... In-depth understanding of ASIC design flow, SoC Verification, Timing Issues, SI and STA using Synopsys PrimeTime. Sound knowledge in communication and networking protocols such as SPI, USB, I2C, UART, PCIe, TCP/IP etc. Passionate, self-motivated and ... - 2017 Apr 21
... In-depth understanding of ASIC design flow, SoC Verification, Timing Issues, SI and STA using Synopsys PrimeTime. Sound knowledge in communication and networking protocols such as SPI, USB, I2C, UART, PCIe, TCP/IP etc. Passionate, self-motivated and ... - 2017 Apr 21
Design Engineer Electrical Engineering
San Jose, CA
... 1.9+ years of experience in System Verilog, Verilog, VHDL, Synthesis, FPGA, STA (Static Timing Analysis), DTA, C, OOPS, Unix, BIST, SCAN, DFT, Validation/Verification. 6 months of exp. In UVM Architecture specifically in Constrained Random ... - 2017 Apr 08
... 1.9+ years of experience in System Verilog, Verilog, VHDL, Synthesis, FPGA, STA (Static Timing Analysis), DTA, C, OOPS, Unix, BIST, SCAN, DFT, Validation/Verification. 6 months of exp. In UVM Architecture specifically in Constrained Random ... - 2017 Apr 08
Engineer, Design, hardware, software, teaching, Linux, Scripting
Santa Clara, CA
... Physical Design Support: Verilog, Physical Knowledge Synthesis, Place and Route, DEF, Static Timing Analysis (STA) and optimization, RC-extraction (SPEF/DSPF files) and back-annotation to Spice netlist, Noise analysis, Yield-awareness routing. ... - 2017 Mar 26
... Physical Design Support: Verilog, Physical Knowledge Synthesis, Place and Route, DEF, Static Timing Analysis (STA) and optimization, RC-extraction (SPEF/DSPF files) and back-annotation to Spice netlist, Noise analysis, Yield-awareness routing. ... - 2017 Mar 26
Design Electrical Engineering
Sunnyvale, CA
... Used PrimeTime for STA. Customized Design of 14b x 14b Multiplier Design and manual routing of Multiplier using Booth-2 algorithm which includes Compressors and Kogge Stone Adder to minimize power and delay. Functional verification using Hspice and ... - 2017 Mar 01
... Used PrimeTime for STA. Customized Design of 14b x 14b Multiplier Design and manual routing of Multiplier using Booth-2 algorithm which includes Compressors and Kogge Stone Adder to minimize power and delay. Functional verification using Hspice and ... - 2017 Mar 01
Engineer Design
San Jose, CA
PROFESSIONAL SUMMARY SKILLS WORK HISTORY THANG PHAM Boise, ID Home: 208-***-**** - Cell: 208-***-**** - acy1tv@r.postjobfree.com Senior Staff ASIC Design Engineer with 15 years of experience in STA (Static Timing Analysis) using Primetime to analyze ... - 2017 Feb 28
PROFESSIONAL SUMMARY SKILLS WORK HISTORY THANG PHAM Boise, ID Home: 208-***-**** - Cell: 208-***-**** - acy1tv@r.postjobfree.com Senior Staff ASIC Design Engineer with 15 years of experience in STA (Static Timing Analysis) using Primetime to analyze ... - 2017 Feb 28
Engineer Software
Santa Clara, CA
... Experience in Simulated annealing, AI algorithms such as A* and branch and bound algorithms Experience March 2016 - May 2016 Senior Member of Consulting Sta, Member of Global Route Team, Mentor Graphics 2013 - 2016 Senior Member of Consulting Sta, ... - 2017 Feb 14
... Experience in Simulated annealing, AI algorithms such as A* and branch and bound algorithms Experience March 2016 - May 2016 Senior Member of Consulting Sta, Member of Global Route Team, Mentor Graphics 2013 - 2016 Senior Member of Consulting Sta, ... - 2017 Feb 14
ASIC Design Engineer
Sunnyvale, CA
... A detailed analysis of hardware cost vs time along with STA was made. Got above average performance metric. 3) ATPG Based Fault Testing and Simulation: (Atalanta and Hope Simulator) (March 2015-May 2015) -Analyzed and compared the k-detectability of ... - 2017 Feb 03
... A detailed analysis of hardware cost vs time along with STA was made. Got above average performance metric. 3) ATPG Based Fault Testing and Simulation: (Atalanta and Hope Simulator) (March 2015-May 2015) -Analyzed and compared the k-detectability of ... - 2017 Feb 03
Engineer Test
Milpitas, CA, 95035
... Experience in DFT STA constraints hand off and debug of timing violations. Expert-level experience in test pattern simulation across timing corners, debug and automation. Good experience in post silicon debug. Worked closely with test engineering ... - 2017 Jan 05
... Experience in DFT STA constraints hand off and debug of timing violations. Expert-level experience in test pattern simulation across timing corners, debug and automation. Good experience in post silicon debug. Worked closely with test engineering ... - 2017 Jan 05