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Design Engineer State University

Location:
San Jose, California, United States
Posted:
May 31, 2017

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UTTAM SAHA

408-***-**** (cell) ac0kqs@r.postjobfree.com San Jose, CA

Physical Hardware Design Role

* Experienced custom, semi-custom and Place & Route circuit design engineer.

* Developed, Characterized, Standard cells libraries released and customer support.

* Custom & semi-custom designed 64bits adder and synthesize control units.

* Designed 40x64 15 ports 6 Writes & 9 Reads custom designed register file.

* Successful tape-outs several microprocessors for server and mobile units. EXPERIENCE

Senior Circuit Design Engineer

Mosys Inc, Santa Clara, CA, Sept. 2016 -

Key Areas: Timing Closure and Clock Tree Synthesis

* Timing closure (Primetime) with AOCV/Derate and Clock tree synthesis with Innovus. Power and signals integrity analysis of EMIR and SIGEM with Voltus. Principal Hardware Design Engineer

Oracle Corp (Montalvo), Santa Clara, California, 2003-Dec. 2016 Key Areas: Register files, Physical Design and Post silicon Details feasibility analysis of 256 128 4-reads x 4-writes register file in 10 FinFET. Feasibility includes timing & area estimation and power saving address decoding.

* Power optimization guidelines for 10nm FinFET standard cells library layout vs drive strength vs leakage power.

* 28% timing improvement (250ps/180ps), power and area (PPA) of 64-bit adder using semi- custom flow (optimized placements & auto routed). Primetime Static timing analysis(STA).

* Designed 40 64 15 ports Register File (Montalvo 3GHz). Architected and developed 6 Writes and 9 Reads with 2 Shadows high performance register file. Read access time 200ps in 65nm. LEC, timing, EMIR, SIGEM, clock analysis and noise verified. Static Timing analysis(STA) completed using Primetime.

* Designed 1-CYCLE 2-STAGE LOOKUP Array for Data Management Unit (1.3GHz)Two synchronous embedded Register files read one followed another during PCI-Express virtual addresses mapping to Systems physical addresses in one clock phase. Both arrays implemented with 6T single port bit cell using 65nm technology. STA with Pathmill.

* Implemented datapath and control blocks using Synopsys IC Compiler II synthesized(P&R) flow. Timing closure, backend EMIR, SIGEM, Clock signal integrity checks.

* Analyzed post silicon electrical validation of microprocessor in server systems varying temp and voltage with performance and power.

Circuit Design Engineer

MIPS TECHNOLOGIES, INC. (Silicon Graphics), Mountain View, California, 1996-2003 Key Areas: Register file, Adder and Standard Cells

* Designed, Implemented and Verified 2 x 288 Prefetch Buffer Register Array in Instruction Cache Interface unit for low power embedded Microprocessors in 130nm.

* Designed 64bit dynamic adder (600MHz) for a low power embedded microprocessor.

* Fast carry was calculated using carry look-ahead and carry-select design. Designed static and dynamic Standard cells and custom macros for Standard cells library. Schematics captured, functional verifications, post layout verifications, timing characterization, physical verification checks and library release. Worked with the mask designers for optimal layouts for PPA & efficient routing. Supported internal customers. Previous Companies

Key Areas: Static and Dynamic Standard cells

* Engineering roles at Silicon Graphics and HAL Computer Systems Designed static, dynamic Standard cells and macros. Schematic capture, pre-layout SPICE simulation analysis in several process corners, functional verification, post layout timing verification and cell characterizations. Physical verification checks and library release. Worked with the mask designers and internal users for optimal layouts for PPA & efficient routing and created datasheet documents for users. PATENT

* "Dynamic Dual Output Latch" (Approved # 11738287) PUBLICATION

* A Process-Portable 64b Embedded Microprocessor with Graphics Extensions and a 3.6GB/sec Interface, by Y. Ho et al., Digest of Technical Papers, 2001 IEEE International Solid-State Circuits Conference, 234 (2001).

TOOLS

Cadence and Mentor schematic and layout tools, HSPICE, ICC, Innovus, Pathmill, Primetime Simplex clock net and Apache & Voltus for EM/IR analysis, XE-CA circuit checker, Cadence ICFB and Magic layout. Formal verification with InnOlogic, LEC and Verplex. PERL scripting.

EDUCATION

M.S. in Electrical & Computer Engineering, PORTLAND STATE UNIVERSITY, Portland, OR. B.S. in Mathematics, PORTLAND STATE UNIVERSITY, Portland, OR. OTHERS

* Volunteer in American Youth Soccer Organization. Volunteer Soccer Referee, AYSO Area Board member and Area 2J Referee Administrator. Recruit, train and mentor volunteer referees. And motivate volunteers keep upgrading refereeing skills and staying involved to referee to help young players in the community.

* Toastmaster International

Ex-President, ex-Area Director.

U S citizen

References will be available upon request.



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