Ted Sun, Ph.D

(Cell) 408-***-**** aczhlv@r.postjobfree.com

Objective: Seeking for a Manufacturing Engineer Position

Linux/Unix IT System and scripting/language experience:

Good experience in Linux System Administration.

Rich experience and strong interest to develop automation utilities on varied design flows for designers to debug easier and rerun in a much shorter time by using Shell, Perl, Python, TCL, C++, R scripting languages.

Strong understanding and knowledge for the Linux/Unix operating system and daily administration work.

Excellent experiences of interacting with EDA vendors and the installation/configuration/usage/mentoring of all kinds of EDA tools in diversified design flows for users.

Research experience:

Solid research work experience and achievement in chip Reliability and Verification areas considering EM, IR, Power, Thermal factors and DRC, LVS.

Several published Journal papers and Conference papers.

Highly interest to continue research works in related or new areas.

Good understanding of VLSI design and flows, semiconductor device and process physics.

Research area covers IC reliability and failure prediction, chip power and electro-migration(EM) analysis, and space physics.

Industry experience:

Strong experience in supporting and developing different physical design flows.

Standard cell design and support for varied operating corners: Layout-view (GDSII), Schematic-view, Abstract-view generator, power-grid library, timing lookup table, timing constraints, fan-out limit, technology and cell LEF, stubs module Verilog.

Design Reliability Analysis: Electro-migration (EM) analysis and fix, Voltage drop (IR) analysis and fix, Power-grid extraction, static and dynamic Power consumption analysis, Chip failure prediction with statistical methodology, Routing material parameters, Thermal analysis.

Physical Design Support: Verilog, Physical Knowledge Synthesis, Place and Route, DEF, Static Timing Analysis (STA) and optimization, RC-extraction (SPEF/DSPF files) and back-annotation to Spice netlist, Noise analysis, Yield-awareness routing.

Physical Verification: To encode DRC and LVS rule decks and debug violations in the integrated GDSII layout for tape-out.

Teaching experience:

Excellent class management and experience to attract student’s learning attention and to monitor student’s understanding and progress.

Take care of different learning abilities, learning approaches, cultures and personalities of students coming from different countries in the world.

Wide range of teaching computer engineering courses including, Computer Algorithm, Csh Script, Bash Script, Ksh Script, Perl, Python, C/C++ Embedded System, JAVA, R, MatLab, Script Languages and Applications, Computer Architecture, Intro. of Computer Engineering, Modern Software Techniques for Electrical Engineers, and Scientific Computing, along with each course’s Lab setting.

Wide range of teaching electrical engineering courses including, Logic Design, Digital Circuit Design, Digital Signal Processing, Probability and Statistics for Engineers, Digital Electronics, Microelectronics Circuit Design and Analysis, Verilog Digital Design, VLSI Place and Route Design, along with each course’s Lab setting.

To lead capstone projects and senior projects for graduate students.

Excellent evaluation feedback from students in different majors and schools.

Curriculum, course description, CLO, PLO and Rubrics writings for the program and courses of Applied Science major.

Education:

Santa Clara University, Santa Clara, CA

Ph.D. in Electrical Engineering, 06/2013

University of Dayton, Dayton, OH

M.S. in Management Science, 08/1994

National Central University, Zhongli, R.O.China

B.S. in Atmospheric Physics – Space physics subgroup, 06/1989

Published Papers:

Ted Sun, Ayhan Mutlu, and Mahamad Rahman, “A New Statistical Methodology Predicting Chip Failure Probability Considering Electromigration,” Microelectronics Reliability Volume 53, Issue 12, Pages 1979–1986, December 2013.

Ted Sun, Ayhan Mutlu, and Mahamad Rahman, “Statistical Electromigration Analysis of a Chip with the Consideration of a Within-Die Temperature Map,” Session C2L-B, IEEE ISCAS, Beijing, May 19-23, 2013.

Ted Sun, Ayhan Mutlu, and Mahamad Rahman, “A New Statistical Electromigration Analysis Methodology that Incorporates Across-Chip Temperature Variation,” Proc. 3rd ASQED Symposium, 2011, Kuala Lumpur, July 19-20, 2011.

Ted Sun, and Ravi Poddar, “Power-grid analysis on SOC-graphics-chip design,” EDN, Pages 36-38, June 10, 2010.

Lin, C. A., L. C. Lee, and Y.J. Sun, “Observations of Pi 2 Pulsations at a Very Low Latitude (L = 1.06) Station and Magnetospheric Cavity Resonances,” J. Geophys. Res., 96, 21105, 1991.

Experience:

International Technological University, San Jose, CA 08/2014 to present

Assistant Chair of Electrical and Computer Engineering Department

Core Faculty

Course curriculum, course description, internship issues, course assignment, course learning outcome

The Chair of bi-weekly internship committee meeting

Lectured the courses: “Algorithm”, “Linux and Python Scripting Language”, “Introduction of Computer Engineering”, “Scientific Computing using R”, “Probability and Statistics using R”, “Signal Processing using MatLab”, “Discrete Mathematics”.

Santa Clara Mission College, Santa Clara, CA 01/2016 to present

Part-Time Faculty

ENGR030 C++ Programming and its Applications in Embedded System

ENGR010 Introduction to Engineering

Sofia University, Palo Alto, CA 01/2017 to present

Embedded Software Application

Object-Oriented Analysis and Design

Python and Shell Scripting Language

UC Berkeley Extension, Belmont, CA 08/2015 to present

Adjunct Faculty

COMPSCI X426.1A UNIX/Linux System Fundamentals

EL ENG X426.1B UNIX/Linux System Administration: Shell, C, and Perl

Integrated Device Technology, San Jose, CA 2006 to 2012

Staff CAD design Engineer

Designed flow automation utilities by using varied scripting languages like: Csh, Bash, Perl, Python.

Analyzed and optimized power consumption, EM and IR-drop for tape-out projects.

Mentored internal designers in using new EDA tools and automation utilities.

Successfully automated the Abstract-Generator flow and the EPS/VSTQRC/Fire and ICE flows on multiple technologies, and 3 different Power analysis tape-out flows.

Supported Automatic Place and Route (APR) Cadence tool.

Awarded for a Technical Talk presentation.

Cadence Design Systems, Inc., San Jose, CA 2001 to 2006

Lead Application Engineer

Provided technical customer support for all Cadence digital and physical design EDA tools.

Provided customers with onsite support, tape-out support and training on multiple EDA tools.

Communicated with sales, marketing, R&D to enhance, evaluate and test on new versions of tools.

Worked with sales to come up with flows to satisfy customer’s design needs and demo to customers.

Integrated Device Technology, Santa Clara, CA 1999 to 2001

Senior Back-End CAD Engineer

Encoded Hercules LVS and DRC decks and tested with designed physical layout/schematic test cases.

Supported physical verification for chip tape-out by using Hercules decks.

Trained all circuit and layout designers in using Hercules DRC/LVS decks and its debugging features.

Finished automated conversion project of Dracula decks to Hercules decks with Shell and Perl scripts.

Successfully implemented Hercules LVS/DRC verification tool for IDT 0.35um full-custom designs of “Ter-Sync DRR FIFO” and “CAM”.

Fritz Inc. 1994 to 1999

Unix System Administrator

Modified and debugged existing HW/SW, maintaining current Sun/HP systems.

Encoded efficient Korn-shell and C-shell scripts to monitor the system performances.

Tools:

Analog: Composer, Virtuoso, Assura, Abstract Generator, Spice

Digital: SOC Encounter, PrimeTime, Verilog-XL, PKS_shell

Verification: Hercules, VoltageStorm, Celtic, Encounter Power System (EPS)

Language: Perl, Shell, Python, C, C++, JAVA, Matlab, R

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