| Resume alert | Resumes 51 - 60 of 139 |
ASIC Design and Verification/ Physical Design and Layout
Fremont, CA
... Performed Static timing analysis STA using TCL script and obtained Setup and Hold time slacks, optimized the design to get positive slack. Parameterizable LMS Adaptive Filter- FPGA (Altera Quartus- II, Qsys, NIOS- II Eclipse, Matlab): • Designed LMS ... - 2017 Sep 20
... Performed Static timing analysis STA using TCL script and obtained Setup and Hold time slacks, optimized the design to get positive slack. Parameterizable LMS Adaptive Filter- FPGA (Altera Quartus- II, Qsys, NIOS- II Eclipse, Matlab): • Designed LMS ... - 2017 Sep 20
Design Electrical Engineering
Santa Clara, CA
... PROJECTS Design, Synthesis and APR of Memory Controller for DDR3 – Implemented the processing logic of a memory controller for DDR3 in RTL, synthesized the design using Design Compiler, performed pre and post synthesis STA using PrimeTime and ... - 2017 Aug 18
... PROJECTS Design, Synthesis and APR of Memory Controller for DDR3 – Implemented the processing logic of a memory controller for DDR3 in RTL, synthesized the design using Design Compiler, performed pre and post synthesis STA using PrimeTime and ... - 2017 Aug 18
skills in editing video tutorial repairing external deffects of cellph
Saratoga, CA
... JANEROL POBLACION WESTE, STA. CRUZ, ILOCOS SUR Contact no.093******** 094******** Email: ac1o04@r.postjobfree.com I.OBJECTIVE To apply the knowledge, skills and attitude I have learned towards work and to enhance them to become more competitive ... - 2017 Aug 06
... JANEROL POBLACION WESTE, STA. CRUZ, ILOCOS SUR Contact no.093******** 094******** Email: ac1o04@r.postjobfree.com I.OBJECTIVE To apply the knowledge, skills and attitude I have learned towards work and to enhance them to become more competitive ... - 2017 Aug 06
Design Engineer
San Jose, CA
... Altera Quartus Other Computing skills: Data structures, OS, MS Office Hardware skills: ASIC, FPGA, ARM, VLSI floorplan, STA, Clock tree synthesis (CTS), CDC, Clock gating, Physical design, RTL coding, Cache design, Advance pipelining, Multicore ... - 2017 Jul 03
... Altera Quartus Other Computing skills: Data structures, OS, MS Office Hardware skills: ASIC, FPGA, ARM, VLSI floorplan, STA, Clock tree synthesis (CTS), CDC, Clock gating, Physical design, RTL coding, Cache design, Advance pipelining, Multicore ... - 2017 Jul 03
ASIC Design Engineer
Sunnyvale, CA
... A detailed analysis of hardware cost vs time along with STA was made. Got above average performance metric. Cache Replacement Policies and Blocking Matrix Method (C++, Simple Scalar Simulator) -Implemented MRU cache replacement policy for heap ... - 2017 Jun 27
... A detailed analysis of hardware cost vs time along with STA was made. Got above average performance metric. Cache Replacement Policies and Blocking Matrix Method (C++, Simple Scalar Simulator) -Implemented MRU cache replacement policy for heap ... - 2017 Jun 27
Management Raw Materials
Hayward, CA
... Intramuros Manila Bachelor of Science in International Hospitality Management Major in Cruise Line Operation in Culinary Arts SECONDARY Sta. Clara Parish School 200*-****-**** Burgos St. Pasay City ELEMENTARY Juan Sumulong Elementary School 199*-*** ... - 2017 Jun 27
... Intramuros Manila Bachelor of Science in International Hospitality Management Major in Cruise Line Operation in Culinary Arts SECONDARY Sta. Clara Parish School 200*-****-**** Burgos St. Pasay City ELEMENTARY Juan Sumulong Elementary School 199*-*** ... - 2017 Jun 27
Logic Design, Digital Design, RTL Design, Verification.
San Jose, CA
... Digital Design, Logic Design, RTL Coding, ASIC Design Flow, SoC Design, Simulation, Synthesis, Static Timing Analysis (STA), Dynamic Timing Analysis (DTA), Time Fixing, Debug, DFT SCAN, Verification, Test Case Generation, Test Plan Development, ... - 2017 Jun 12
... Digital Design, Logic Design, RTL Coding, ASIC Design Flow, SoC Design, Simulation, Synthesis, Static Timing Analysis (STA), Dynamic Timing Analysis (DTA), Time Fixing, Debug, DFT SCAN, Verification, Test Case Generation, Test Plan Development, ... - 2017 Jun 12
Engineer Design
San Jose, CA
... More than eight years of experience in ASIC Back- end in Synthesis, insert scan chain for DFT/JTAG, static timing analysis(STA), power planning, floor-planning, place & route, clock tree synthesis(CTS), timing closure, SI analysis, LVS/DRC/Antenna ... - 2017 Jun 10
... More than eight years of experience in ASIC Back- end in Synthesis, insert scan chain for DFT/JTAG, static timing analysis(STA), power planning, floor-planning, place & route, clock tree synthesis(CTS), timing closure, SI analysis, LVS/DRC/Antenna ... - 2017 Jun 10
Design Electrical Engineering
Santa Clara, CA
... DRC, LVS, & QRC was done using Cadence Virtuoso and Composite Schematic Cadence Encounter was used for floor planning, placing and routing of the implementation STA is performed using Synopsys PrimeTime. Power & area report is generated using Design ... - 2017 Jun 06
... DRC, LVS, & QRC was done using Cadence Virtuoso and Composite Schematic Cadence Encounter was used for floor planning, placing and routing of the implementation STA is performed using Synopsys PrimeTime. Power & area report is generated using Design ... - 2017 Jun 06
Design and Verification Engineer
San Jose, CA
... and Power Engineering (RTM Nagpur University, India) GPA 3.50 TECHNICAL SKILLS: Skills: ASIC, CMOS, RTL Design, Synthesis, Testing, Verification & Validation, AXI Bus Protocol, SPI Protocol, Computer Architecture, Static Timing Analysis (STA). ... - 2017 Jun 05
... and Power Engineering (RTM Nagpur University, India) GPA 3.50 TECHNICAL SKILLS: Skills: ASIC, CMOS, RTL Design, Synthesis, Testing, Verification & Validation, AXI Bus Protocol, SPI Protocol, Computer Architecture, Static Timing Analysis (STA). ... - 2017 Jun 05