Youcef Bourai

408-***-****

acytvq@r.postjobfree.com

Objective

Seeking a C/C++ software development position in the software industry Expertise

** ***** ********** ** ******* algorithm design and implementation for Electronic Design Automation (EDA) of VLSI chips in C/C++

Deep knowledge in Computational Geometry, Graph Theory, multi-threading and Optimization algorithms in linear programming and integer linear programming. Experience in Simulated annealing, AI algorithms such as A* and branch and bound algorithms

Experience

March 2016 -

May 2016

Senior Member of Consulting Sta, Member of Global Route Team, Mentor Graphics 2013 - 2016 Senior Member of Consulting Sta, Mentor Graphics

Member of extraction team within the Place and Route Group

Key contributions: Multi-threading the extraction

ow by adopting a producer-consumer model, Cleaning overlapping shapes to optimize the RC parasitic network, using Computa- tional Geometry algorithms

2010 - 2013 Senior Member of Consulting Sta, CADENCE Design System

Key contribution: Multi-Threading the Parasitic Extraction

ow of the QRC tool. 2003 - 2010 Senior R&D Engineer and Project Leader, VLSI Routing Technology, SILVACO Systems

Designed and implemented Global Router, based on minimum steiner tree in a graph using A* algorithm

Designed and implemented Track Assignment based on nding maximum clique on an inter- val graph as well as a scan chain based on a TSP (Traveling Salesman Problem) algorithm

Designed and implemented a spacer that xes the distance between routes, using a triangu- lation technique (Voronoi Diagram-like) to compute the shortest distance between a set of 2-D points.

2000 - 2003 Senior R&D Engineer, SYNOPSYS

Contributed to the following product lines: FlexRoute, Floor Plan Compiler (FPC), and Columbia Chip Assembly.

Maintained and enhanced the FlexRoute routing tool;

Implementation of Pin Assignment in FPC, using dynamic programming technique. 1

Research

1998 - 1999 Visiting Researcher, Department of Electrical Engineering, University of Washington

Developed a C/C++ (under Xwindow) program that automatically recycles analog layout to enable technology migration, using Linear Programming (LP) formulation. 1997 - 1998 Visiting Researcher, Department of Electrical and Computer Engineering, University of Iowa

Developed a program to automatically detect symmetrical components in a layout of analog circuits.

1991 Visiting Researcher, VLSI Research Group, University of Waterloo

Completed research under renowned Professor M. Elmasry. Integrated STAIC, an analog circuit synthesis tool into the Cadence design

ow using the Cadence built-in languages ILL and SKILL.

Education

1990 M.S. in Microelectronics, Computer Aided Design with honors, CDTA, Algeria 1986 B.S. in Computer Science. University Houari Boumediene of Science and Technology, Algiers, Algeria

Skills

Programming C, C++, Tcl/Tk

Operating

Systems

UNIX/Linux

Pro ling Tools Sun Studio, Vtune, Inspector, Valgrind. Publications

Y. Bourai and C.-J.R. Shi, Layout Compaction for Yield Optimization via Critical Area Minimization, IEEE/DATE 2000, pp. 122-125, Paris, 2000.

Y. Bourai and C.-J.R. Shi, Symmetry Detection for Automatic Analog-Layout Recycling,IEEE/ASP-DAC99, pp.5-8, Honk Kong, 1999.

Y. Bourai, N. Izebiudjen, Y. Bouhabel, A. Tafat, " A New Approach for an AHDL Based on Systems Semantics", IEEE/ASP-DAC97, pp. 201-206, Tokyo, Japan, 1997.

Y. Bourai and M. A. Makhlou, "A Balanced Technique to Bisect an Ordered Set",International Conference on Microelectronics, 1996, Egypt.

Y. Bourai et al, " An Analog Synthesis Tool with a Hardware Description Language Based on System Semantics", International Conference on Microelectronics, 1996, Egypt.

Y. Bourai and N. Izeboudjen, " A Analog Cell Generator Using Functional Paradigm "International Conference on Microelectronics, 1995, Malaysia.

Professional Activities

Reviewer of IEEE/Design Conference Automation (DAC) and IEEE/ISCAS conferences 2

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