Design Engineer Electrical Engineering

SAI AKHIL AYYAGARI

San Jose, CA, USA Phone: 737-***-**** Email: aczpyi@r.postjobfree.com

Summary

ASIC/FPGA Design Engineer with 1.9+ years of exp. in RTL Design/Debug/Verification/Testing/Board Bring up.

1.9+ years of experience in System Verilog, Verilog, VHDL, Synthesis, FPGA, STA (Static Timing Analysis), DTA, C, OOPS, Unix, BIST, SCAN, DFT, Validation/Verification.

6 months of exp. In UVM Architecture specifically in Constrained Random Verification, Scoreboard.

6 months of experience on SoC (Zynq ZC706, XC30) chips with working knowledge on PS (Processing System) and PL (Programmable Logic) and 1 year of experience on Virtex ML605 Board.

Knowledge in AHB, APB Buses, Perl, TCL, SVA, Functional Coverage, SPI, UART/RS232, TCP/IP, VIP.

Education

MS. Electrical Engineering (Digital VLSI), San Jose State University (SJSU), GPA – 3.7 May 2017

Relevant Courses – ASIC CMOS Design, Computer Architecture, Linear System Designs, Advanced FPGA Design for DSP, Semiconductor Devices, Digital Design for Synthesis, SoC Design and Verification.

Bachelor’s in Technology Jawaharlal Nehru Technology University (JNTU), GPA – 3.7 May 2014

Skills

Programming Languages - C, Verilog, VHDL, Assembly, System Verilog, OOPS, Perl, UVM 1.2.

EDA Tools - Orcad, ISE, Quartus, ModelSim, MATLAB, Synopsys VCS, NC Verilog, Vivado, SDK.

Devices - Zynq ZC706.

Work Experience

Sodick America Corporation., USA. (Hardware FPGA Engineer Intern) June 2016 – Dec 2016

Board Bring Up – Implemented BIST (Built in Self-Test) and TRD program on the custom ZC30 board for the board bring up using Vivado and SDK tools. During the process resolved the issues in the hardware design.

AXI4 Slave Lite Interface – Designed and Simulated an AXI4 slave lite interface bridge between the processor and the FPGA in RTL (Verilog). The design was verified using a loopback test using BFM (Bus Functional Model).

FSBL Fallback Multiboot – Implemented the multiboot feature by programming the PS (Processing System) FSBL (First Stage bootloader) and issuing a soft reset.

ICS LTD., India. (Hardware Design Engineer) June 2014 – August 2015

Implemented an FSM in Verilog which dynamically reconfigures the FPGA during the Run time.

The FSM sends a sequence of commands to the ICAP (Internal Configuration Access port) controller primitive to assert the PROGRAM_B pin (which resets the chip) along with registering the contents into WBSTAR register.

Validated the past design on the new custom board and made changes to the UCF Files according to the requirement.

Involved in the FPGA Design cycle which includes Board Design, Fabrication, Board Verification (Debugging), Physical Netlist Verification.

Course Projects – (Additional Projects available on LinkedIn)

Bus Master for Network on Chip Bus– Designed a Bus Master for Network on Chip, which communicates between the sub blocks (CRC) of an SoC (System on Chip) in RTL (System Verilog). The bus supports Incremental bursts up to 128 bytes and was synthesized at 200 Mhz using Synopsys VCS tool.

CRC Block Generator – Designed a sub block of SoC (System on Chip) Cyclic Redundancy Check (CRC) generator modules which include Reverse logic, CRC Engine, modes of operation in System Verilog for a NXP Microcontroller.

VIP of UART in UVM [In progress] – Developing the UVM test bench to verify the UART’s Tx protocol. The Scoreboard will be checking for Baud Rate, Parity bit, # of bits, Start and Stop bit.

VIP of an Arbiter in UVM [In progress] – Developed the UVM framework from scratch, which configures itself during run time. Designing a Low Power Bus Arbiter in System Verilog using VCS Synopsys Tool.

FIFO Verification in UVM – Developed the UVM test bench to verify the FIFO functionality. The scoreboard checks for data, full and empty flags.

Designed NIOS 2 Architecture – Designed Altera Nios 2 Processor architecture in Verilog which avoids data hazards, structural hazards and control hazards by having a hazard detection unit in the architecture.

Hardware Gaussian Noise Generator using Box Muller – Designed 64-bit Gaussian Noise Generator using Box Muller method and optimized it to work at 300 Mhz, 200 Mhz using 2 Flag push model of pipelining in Verilog using VCS.

Optimization of High Speed Adders - Designed a High-Speed Carry Look Ahead, Ripple Carry Adder with Area, Power, and Performance as key parameters. Performed Static Timing Analysis (STA) and Dynamic Timing Analysis (DTA) in Verilog using VCS Synopsys Compiler.

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