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Hardware Engineer

Location:
San Jose, California, United States
Salary:
65000
Posted:
April 21, 2017
Email:
aczxag@r.postjobfree.com

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Sindhu Maturi

San Jose, CA - *****; +1(832)*** ****; aczxag@r.postjobfree.com

https://www.linkedin.com/in/sindhumaturi

Summary

Proficiency in HDL coding such as Verilog, VHDL and good programming skills in C, C++ and python.

Experience with simulation, schematic and layout design tools like Cadence Virtuoso, ModelSim, Xilinx, PSpice, Synopsys etc.

Capable of designing CMOS, RF Analog and Digital Circuits.

Hands-on experience with Altera Cyclone IV-E and ARM Cortex-M, 8051/8052, PIC microcontrollers using Keil, MPLAB X IDE.

Experience with oxidation, reduction, RTP, wet etching, photolithography on a Silicon wafer in fabrication laboratory.

Worked with lab test equipment such as oscilloscopes, DMM, signal generators, spectrum analyzers etc.

In-depth understanding of ASIC design flow, SoC Verification, Timing Issues, SI and STA using Synopsys PrimeTime.

Sound knowledge in communication and networking protocols such as SPI, USB, I2C, UART, PCIe, TCP/IP etc.

Passionate, self-motivated and quick learner with strong communication and team skills. Education

Graduation: University of Houston, Houston, TX Dec 2016 Master of Engineering in Electrical Engineering (Specialization in Electronics and Computer Engineering) GPA: 3.64 / 4.00 Undergraduation: Vignan’s Lara Institute of Technology and Science (VLITS), Vadlamudi, India May 2015 Bachelor of Technology in Electronics and Communications Engineering GPA: 3.78 / 4.00 Work Experience

Lab Assistant Houston, Texas

College Of Technology - University of Houston Aug. 16-Dec. 16

Demonstration of lab experiments for Digital Systems, Semiconductor devices Laboratories (sophomore level). Prominence on implementation of digital logic circuits using various ICs and other circuits involving basic electronic components.

Graded students’ homeworks, exams and lab reports. Internship (Embedded Systems Lab – VLITS) Vadlamudi, India Gesture Controlled Rover Mar. 14-May 14

Designed a rover that can be controlled by hand movements through 433 MHz RF communication and ADXL335 accelerometer.

Programmed an AT89S52 Microcontroller in C using Keil to process movements of hand and corresponding motion of the rover. Projects

Performance Analysis of Cache Configurations using SimpleScalar (Solo) Houston, Texas (Oct. 16-Dec. 16)

Studied and analyzed the effect of cache size, block size and associativity on the cache performance.

Inferred the best possible configuration using SimpleScalar and SPEC2000 Benchmark suite. Butterworth Low-Pass Filter Design in CMOS Technology (Solo) Houston, Texas (Oct. 16-Dec. 16)

Designed a Butterworth Low-Pass Filter with a 3-dB Bandwidth of 1.5 MHz using a two stage op-amp circuit.

Implemented design using Cadence Virtuoso. DRC and LVS are verified. Schematic and post layout simulation results are observed. Secure FPGA-based Student ID Verification System (Team Leader) Houston, Texas (Sep. 16-Oct. 16)

Designed a system that authenticates the user by checking the user input to its secret mapping to the student ID.

Coded the modules in Verilog, verified functionality using ModelSim and is implemented on Altera FPGA using Quartus. Design of RF Transmission System in 180nm CMOS Technology using Cadence (Team Leader) Houston, Texas (Mar. 16-May 16)

Designed Low noise RF Amplifier, Gilbert Mixer and Voltage Controlled Oscillator.

Implemented the circuit using Cadence Virtuoso and obtained transient response, output spectrum and phase noise.

Measured S parameters, Noise Figure, Stability Factor, 1dB Compression and 3rd Order Intermodulation Intercept Point. 16 Bit RISC Processor (Team Member) Houston, Texas (Oct. 15-Dec. 15)

Designed a 16-bit general purpose RISC Processor with 16 instructions and 16 general purpose registers.

Coded these modules in Verilog and synthesized on a 600nm process using Model Sim and Cadence Virtuoso. Single Precision Floating Point Multiplier using Vedic Aphorism (Team Leader) Vadlamudi, India (Apr. 15-May 15)

Designed a Floating point multiplier based on an algorithm, which reduces the propagation delay and power consumption.

Implemented this design using VHDL. Simulations are performed using Xilinx ISE and results are observed. Micro-controller based Dam Gate Control (Team Leader) Vadlamudi, India (Jan. 14-Mar. 14)

Implemented a small working model of a dam using water level sensors, microcontroller, a DC motor driver and a DC motor.

Programmed an AT89S52 microcontroller in C using Keil software. Dam gates are driven by dc motor using motor driver L293D. Skills

Programming / Hardware Description Languages: C, C++, Python, Verilog, VHDL Engineering Applications: Cadence Virtuoso, Keil μVision, LT Spice, Pspice, MATLAB, Multisim, OrCAD, Proteus, Xilinx, ModelSim, MPLAB X IDE, Quartus, Synopsys PrimeTime, Silvaco, Visual Studio Operating Systems: Windows, Linux

Courses: VLSI Design, CMOS Analog Integrated Circuit, RF and microwave electronics, Integrated Circuit Engineering, Advanced Process Integration for VLSI, Analog and Digital Communications, Circuit Theory, Digital Logic Design, Embedded Systems, Advanced Computer Architecture, Digital Control systems, Principles of Internetworking, Computer Networks Involvement

Indian Society for Technical Education (Member – Students Chapter) Vadlamudi, India (July 12 – May 14)

Organized several technical workshops and guest lectures by pioneers in respective fields



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