Engineer Test

VANI S Contact Details : +1-925-***-****

Email ID : ********@*****.***

LinkedIn : https://in.linkedin.com/in/vani-s-4a1787a

OBJECTIVE:

Seeking challenging job opportunities with an organization that promotes the idea of continuous learning, and good teamwork, where I can achieve multidimensional professional growth through application of technical skills. Innovate and implement the latest techniques, methodologies and practices in Semiconductor Industry.

EXPERIENCE SUMMARY:

10 years of experience in VLSI front-end ASIC design with profound expertise in the following areas.

Excellent experience in Test Architecture for all Mobile Audio projects at NXP Semiconductors.

Experience in synthesis setup for complex multimillion gate design to meet the timing margins as per the specification. Worked on both bottom-up and top-down approach on understanding the design needs.

Expert-level experience in scan insertion requirements and implementation. Have good understanding of the DRC rules and RTL with DFT.

Experience in flow creation and constraints mapping for Formal Verification.

Experience in DFT Validation flow using scan netlist to verify the test structures like JTAG even before ATPG. Good experience in implementing sanity and connectivity checks for scan chains and other test control structures.

Good experience in IO test strategy, implementing Boundary scan and IO tests for pin limited designs.

Expert-level experience in Automatic test pattern generation (ATPG) for fault models like stuck-at, transition, iddq, path delay and small delay defect. Excellent in coverage analysis and debug.

Good experience in memory testing for all in-house and third party memories like MBIST. Experience in reducing memory test time and test volume.

Experience in DFT STA constraints hand off and debug of timing violations.

Expert-level experience in test pattern simulation across timing corners, debug and automation.

Good experience in post silicon debug. Worked closely with test engineering teams.

Experience in mixed signal test implementation and simulations.

Hands on with IDDQ diagnosis, LBIST implementation and test point insertion flow from Mentor Graphics.

Have good knowledge and experience with low power EDT and low power test implementation techniques.

TECHNICAL SKILLS:

Coding Languages: Verilog HDL, VHDL, C

Scripting Languages: Perl, TCL, Shell Scripting

Operating System: Linux, Microsoft Windows XP, Solaris

EDA Tools and Test formats:

Synopsys Tools - DC and DFTCMAX, TETRAMAX, VCS, FORMALITY

Mentor Graphics Tools -DFTAdvisor, MBISTArchitect, YieldAssist/Tessent Diagnosistics, FASTSCAN,TESSENT

Cadence Tools - Conformal, RC, ModelSim

Atrenta Spyglass

Knowledge of SPEA and Verigy tester file formats

EDUCATIONAL QUALIFICATION:

Qualification

Institute

Percentage Year of Pass out

B.E (ECE)

Visvesvaraya Technological University (VTU)

78 (aggregate)

2006

WORK EXPERIENCE:

Senior Technical Lead

NXP Semiconductors, Bangalore, India

Aug 2012 - Nov 2016

Role: DFT lead for all Mobile Audio projects within NXP, BU S &C, Project Line Mobile Audio.

Responsibilities:

Completely owned responsibility of DFT infrastructure and RTL implementation for 140nm,90nm and 65nm designs.

Generated the top-level RTL and test structures.

Owned DFT design and test strategy including IOs.

Reduced test time of a memory from 1.4s to 0.56ms on careful analysis of BIST.

Implemented shared bist and production test flow for in-house memories.

Implemented low power DFT techniques to save test power. Generated VCDs for RedHawk analysis.

Implemented and executed IDDQ Diagnosis flow.

Created test point insertion flow to fix modules with low coverage based on hierarchical coverage reports.

Coverage Analysis carried out to meet DfX coverage goals of 99% test coverage and 98% fault coverage.

Worked on Mixed signal tests and simulations.

Involved in Pre & Post silicon support. Travelled to Europe and worked closely with TPE teams.

Actively participated and contributed in customer return debug and support. Was member of 8D team.

Have also worked on MRA2 release of personal health project which was a low power design. Had a great opportunity to learn more on mixed signal tests.

Module Lead

Mind Tree, Bangalore, India

Feb 2011 - Jul 2012

Role: Consultant DFT support Engineer for a SoC, TI-Dallas.

Responsibilities:

Was supporting DFT activities like redump of ATPG patterns for a 90nm SoC that was taped out.

Simulating the same with new constraints if failure seen on tester.

Learnt JTAG and BSDL file validation flow using customer tool (Validate).

Module Lead

Mind Tree, Bangalore, India

Dec 2010 - Jul 2011

Role: Consultant DFT Lead for a GPU sub-chip, TI, Bangalore.

Responsibilities:

Worked on 28nm technology, 5million gate count with approximately 100K flops.

Implemented unique DFT architecture with modular codecs.

Created DFT RTL Verification-Hookup checks flow. Clock shaper and P1500 controller programmation was verified at RTL level.

Owned complete scan insertion and atpg for three cores.

Guided scan stitching done on inputs from backend. Developed Atpg scripts for standalone core test and top-level core test.

Carried out Coverage analysis for stuck-at, transition (LOC) and iddq fault modes.

Executed Atpg and pattern simulation in timing and notiming corners.

Created and implemented path delay testing.

Successfully met DFT coverage goals for stuckat and transition modes met for individual cores and from top-level.

Debugged several issues related to simulation failures in notiming and timing.

Identified several RTL bugs related to DFT at initial stages and fixed the same.

Supported STA team by providing proper DFT constraints.

Developed single elaboration flow using NCSIM to save disk space.

Senior Engineer

Mind Tree, Bangalore, India

Sep 2008 - Dec 2010

Role: Consultant DFT Engineer for a Video/Imaging hardware acceleration sub-system, display sub-system and graphics accelerator -TI, Bangalore.

Responsibilities:

Worked on 65 nm technology, 40 nm technology with 250k flops.

Understanding the DFT architecture was very challenging which included P1500 controller.

Supported two different netlists with same RTL targeted with varying memory sizes including Compression logic (100X).

Owned scan insertion and atpg activities.

Carried out Coverage analysis for stuck-at, transition (LOC) and iddq fault modes.

Owned Atpg and pattern simulation in timing and notiming corners.

Suggested Path Delay testing due to critical paths in the design. Extracted the paths from PT sessions and generated the test patterns.

Achieved the DFT coverage goals for stuckat, transition and iddq fault models.

Have carried out power aware atpg. Scan mode power saving techniques tested.

Worked on PT shell to do power analysis in shift and capture modes.

Debugged several issues related to simulation failures in notiming and timing.

Identified RTL bugs related to DFT and reported the same.

Detailed analysis on dead logic was carried out to achieve coverage goals.

Supported totally four different test modes.

Customer specific memory testing (PBIST) flows were also carried out which included generation and validation and hookup checks.

Developed single elaboration flow using VCS to save disk space.

Senior Engineer

Mind Tree, Bangalore, India

Feb 2008 - Aug 2008

Role: DFT Lead for Internal project, Mind Tree.

Responsibilities:

Developed the Test plan based on the requirements for ten different IPs.

Manually edited the netlist by adding test logic to resolve DRC violations reported during scan insertion

Handled bidirectional pins in the design.

Patterns generated for stuck at and transition faults and verified the same through simulations

Engineer

Mind Tree, Bangalore, India

Jun 2007 - Jan 2008

Role: Consultant Engineer for all front-end work and DFT for TV Processor Chip, NXP, Bangalore.

Responsibilities:

Worked on 90 nm technology.

Involved at core level in synthesis and DFT related activities.

Performed DFT validation and pattern generation.

Coverage target of 99% fault coverage attained for many core level modules which was a major task.

Resolved issues related to redundant, tied and aborted faults.

Executed Synthesis & scan-insertion of core level modules.

Developed scripts for project related tasks in Perl & TCL.

Performed Formal Verification using Cadence Conformal and Synopsys Formality tools.

Used spyglass for rules checking.

Engineer

Mind Tree, Bangalore, India

Dec 2006 - May 2007

Role: Consultant Engineer for all front-end work and DFT for Video Picture improvement IC–NXP, Southampton.

Responsibilities:

Worked on 90 nm technology

Synthesis done at core level using Synopsys Design Compiler.

Involved in Scan insertion and ATPG

Involved in Formal Verification between RTL & synthesized netlist and further between synthesized and scanned netlist. Used Cadence Conformal. Involved in analyzing the incompetency of Conformal to detect the optimization done by Synopsys DC tool during synthesis.

Developed the scripts for running the entire flow with a single run

Pattern generation using Customer proprietary tools. Attaining 99% test coverage for most of the modules.

Used Spyglass for rules checking.

Engineer

Mind Tree, Bangalore, India

Sep 2006 - Nov 2006

Role: Engineer for OCP Modeling, Internal project.

Responsibilities:

Prepared Requirements and Specification document on understanding OCP.

Prepared Design document.

Modeled in Verilog.

Undergraduate Project

DRDO,LRDE, Bangalore, India

Feb 2005 - Apr 2006

Linear Frequency Modulated Digital Pulse Compression in RADARs Using Matlab.

The aim of the project was to increase the radar range. It was successfully tested for both single and multiple targets. As an enhancement of the project it was also coded in c and implemented on TMSC6713 processor.

PROFESSIONAL ACHIEVEMENTS:

Won 3rd prize in NEXPLORE, innovation competition at NXP Semiconductors in 2013. As a token of

appreciation, was sponsored to attend workshop at Vlerick Business School at Leuven, Belgium.

Presented a paper on SYPGLASS DFT at DE Conference, NXP Semiconductors, Bangalore, 2012.

Presented a poster on IDDQ DIAGNOSIS at DFT Internal Conference at Hamburg, Germany, 2016.

Abstract on IDDQ DIAGNOSIS was selected at Mentor Graphics U2U Conference, Bangalore, 2016.

ADDITIONAL COURSES ATTENDED:

VLSI System Design (an ETYE Course) at M.S. Ramaiah School of Advanced Studies, Bangalore,

2005-2006.

Participated in Innovation and Business workshop at Vlerick Business School, Leuven, Belgium,

2013.

CMOS Training at NXP Semiconductors.

AREAS OF INTEREST: Design for Testability, STA, Test Time and Test Volume Reduction.

Personal details and References can be provided based on request.

I hereby declare that the information furnished by me is true to the best of my knowledge & belief.

Place: San Jose

Date: 02-01-2017

Vani S

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