Engineer Design

PROFESSIONAL SUMMARY

SKILLS

WORK HISTORY

THANG PHAM

Boise, ID

Home: 208-***-**** - Cell: 208-***-**** - *************@*****.*** Senior Staff ASIC Design Engineer with 15 years of experience in STA (Static Timing Analysis) using Primetime to analyze and close timing on large and complex designs in 28nm, 40nm, and 130nm. Extensive experience in developing complex timing constraints for block, top, and I/O. Place and route multiple blocks with very high performance requirements. In-depth knowledge about physical design flow, synthesis, floorplaning, powerplanning, PSYN, CTS, and route.

- Expert in Primetime

- Highly experience in development

Top Level Timing constraints

IO constraints

- Proficient in Perl and Tcl

- Proficient in Formality and Conformal

- Experience in GCA

- Extensive knowledge in Physical Synthesis

- Highly proficient in Design Compiler

- Proficient in Place and Route (ICC2)

- Advanced Critical thinking in timing closure

- Proficient in verilog and Hspice

- Experience in Modelsim and ncverilog

2005 to Current Senior Staff ASIC Design Engineer

Marvell Technology Company – Boise, Idaho

Led and managed synthesis design team to work on a large and complex design in 28nm. The design is about 80mm2 with 3 PLLs at top and multiple PLLs at various block levels and IPs.

Placed and routed very high performance blocks i.e. 3Ghz in 28nm process Technical timing lead on multiple ASICs in 28nm working with external vendor Developed and created complex timing constraints for blocks and top level

- DDR PHY and controller

- USB2_PHY and controller

- CORTEXA53, CORTEXR4, and CORTEXM3

- GC7000L

Developed and created stringent I/O timing constraints for large complex designs

- RGMII

- Bootspi

- SDMMC

- LVDSAFE

- COMPHY

Performed synthesis on complex 28nm ASIC using DC-Topo from Synopsys Performed GCA tool (Synopsys) to check complicated timing constraints Performed Static Timing Analysis using Primetime and Primetime-SI

- Achieved timely timing closure on designs

- Functional designs with first tape-out

Ran LEC (Logical Equivalency Checking) RTL to gates using Formality and Conformal. Technical lead on number of 40nm ASIC designs. Primary responsibilities:

- Main interface with customer and vendors

- Setup and maintain ASIC design enviroment

- Analyze and resolve all ASIC timing issues

- Generate SDF and simulate back-annotated netlist

- Run weekly project meeting and keep track all issues Traveled extensively to Shanghai, China and Penang, Maylaysia to train and work with vendor and engineers on physical designs

Mentored junior engineers and new hires to better improve the competency and efficiency of all staff.

EDUCATION

01/2000 to 12/2005 IC Hardware Engineer

Agilent Technologies – Boise, Idaho

Technical leads on many ASIC designs in 130nm process. Primary responsibilities:

- Main interface with customer and vendors

- Setup and maintain ASIC design environment

- Analyze and resolve all ASIC timing issues

- Generate SDF and simulate back-annotated netlist

- Run weekly project meeting and keep track all issues 1989 to 1999 Hardware Engineer

Hewlett Parkard Company – Boise, Idaho

Designed differential pad drivers for controller chip in printer Formulated technology roadmap as part of a divisional procurement strategy for power and servo chips

Provided technical leadership in the selection and recommendation of suppliers for disk drives

Served as technical liaison between design and manufacturing organizations 1999 Master of Science: Electrical Engineering

University of Idaho - Moscow, Idaho

1989 Bachelor of Science: Electrical Engineering

University of Washington - Seattle, Washington

US citizen

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