ASIC Design and Verification/ Physical Design and Layout
Resume:
LAVANYA
JAGARLAMUDI
ac2ehl@r.postjobfree.com
https://www.linkedin.com/in/lavanya- jagarlamudi
(510 936- 4959 OBJECTIVE:
Seeking a Full- time position in the field of ASIC Design and Verification utilizing my skills and knowledge to build experience
working
with
professionals
while
being
resourceful,
innovative
and
flexible. TECHNICAL
SKILLS
Programming
Languages:
C,
C++,
Java/J2EE,
Oracle,
Perl,
Python,
Verilog
HDL,
System
Verilog,
UVM. Design
Tools:
Matlab/Simulink,
Xilinx
ISE,
Synopsys
(Design
Compiler),
Design
Vision,
Altera
Quartus
II,
ModelSim,
PSPICE, Cadence
Virtuoso,
Cadence
Encounter,
Si-
Soft,
Oscillators,
Pattern
generators. Operating
Systems:
Unix/Linux,
Windows Technical
Skills:
Logic
Design,
SoC
Design
and
Verification,
Low
power
design,
Physical
Design
and
Layout,
Static
Timing Analysis,
Design
for
testability(DFT),
Constraint
Random
Verification,
Assertion
based
Verification
using
System
Verilog, Functional
and
Code
coverage,
Analog
IC
Design. EDUCATION
Masters
in
Electrical
Engineering
GPA:
3.53
May’17 San
jose
State
university,
San
jose Bachelors
in
Electrical
and
Electronics
Engineering
GPA:
3.73
May’12 Acharya
Nagarjuna
University,
India
RELEVANT
COURSEWORK
Digital
Design
and
Synthesis,
ASIC
CMOS
Design,
Advanced
Computer
Architecture,
SoC
Design
and
Verification
using
System Verilog,
Implementation
of
DSP
using
FPGA,
Analog
Integrated
Circuit
Design,
Semiconductor
Devices,
Linear
System
Theory, Network
Theory,
C++
programming,
Data
Structures. EXPERIENCE
Graduate
Teaching
Assistant,
San
jose
state
university
(9
months)
Aug’16
–
May’17
• Helped
in
preparing
lecture
notes
and
course
assignments
for
Statistics
and
data
analysis.
• Assisted
students
in
using
modeler
tools
like
IBM
SPSS,
SAS
etc. Systems
Engineer,
Tata
Consultancy
Services,
India
(3.1
years)
Jun’12
–
July’15
• Developed
web
applications
(https://www.proximus.be)
using
Java/J2EE,
Oracle,
PL/SQL.
Implemented
and scheduled
batch
processing
and
automation
scripts
for
functional
testing
using
PERL
and
Shell
scripting.
Involved
in auditing
and
Code
debugging.
RELATED
PROJECTS
Implementation
of
MOC
for
Nuetron
Transportation
equations
(Toshiba
Library- 250nm-
2.5V-
Synopsys):
• Implemented
an
effective
floating
point
unit
(Single
and
double
Precision)
using
parallel
and
pipelining
methods
(Used
Karatsuba
algorithm
for
multiplier
and
dual
path
algorithm
for
Floating
point
adder).
Pipelined
the
design
to improve
clock
frequency.
Modified
the
equations
for
low
latency.
• Implemented
FIFO
and
built
in
SCAN
test
for
the
floating
point
unit. Design
and
verification
of
CRC
Block
with
NOC
(as
bus
master):
(system
Verilog)
• Designed
and
synthesized
the
CRC
(Cyclic
Redundancy
Checksum)
block
with
NOC,
that
generates
16/32
bit
CRC code
for
error
detection
and
provides
a
programmable
polynomial
and
other
parameters
required.
• The
Bus
Master
NOC
connected
CRC
engine
expands
on
to
the
existing
CRC
design
enhancing
the
NOC
controller,
to be
a
bus
master.
Design
of
bidding
arbiter:
• Implemented
a
bidding
arbiter
in
System
Verilog
which
can
handle
4
masters
and
4
slaves.
• Synthesized
the
design,
Performed
the
static
timing
analysis
and
the
design
was
checked
for
setup
and
hold
time violations.
UVM
based
verification
of
an
8
bit
ALU
module:
• Performed
verification
of
an
8- bit
arithmetic
logic
module
using
constraint
random
testing
and
UVM
libraries.
• Different
sequences
were
generated
to
detect
the
faulty
ALU
DUT. Five
stage
pipelined
NIOS- II
Processor:
• Implemented
the
5- stage
pipelined
NIOS2
processor
in
Verilog
with
Data
Forwarding,
to
overcome
hazards.
• Executed
dot- product
and
Factorial
benchmark
programs
having
R,
I,
J
type
instructions. Place
and
Route
of
floating
point
adder
and
multiplier:
• Generated
the
net
list
file
and
Synopsys
design
constraints
file.
Setting
design
environment
with
timing
and
library files.
Executed
the
design
flow:
Floor
plan,
Power
rails,
Placement,
Clock
Tree
Synthesis,
Route,
Verifying
timing,
GDSII extraction.
Box
Muller
Theorem
for
random
number
distribution:
• Implementation
of
Box- Muller
Theorem
in
Verilog
to
convert
two
random
numbers
to
an
approximation
of
a
Gaussian random
number
distribution.
Static
timing
analysis
for
4
different
types
of
64- bit
adders:
• Designed
and
synthesized
4
different
adders:
Ripple
carry
adder,
Carry
look
ahead
using
2- Level
P- G
generator, Carry
Select
adder
using
equal
and
unequal
bit
groups.
• Prepared
test
benches
in
Verilog,
TCL
to
verify
the
design.
Performed
Static
timing
analysis
STA
using
TCL
script
and obtained
Setup
and
Hold
time
slacks,
optimized
the
design
to
get
positive
slack. Parameterizable
LMS
Adaptive
Filter-
FPGA
(Altera
Quartus- II,
Qsys,
NIOS- II
Eclipse,
Matlab):
• Designed
LMS
filter
with
data
memory,
implemented
as
a
circular
buffer
(to
reduce
traffic)
and
dual
port
memory implemented
as
coefficient
memory
to
update
coefficients
in
RAM
blocks.
• Two
multipliers
with
saturation
and
rounding
are
used
as
LMS
module
and
a
pipelined
FIR
module
as
filter
engine. Test
vectors
are
generated
in
MATLAB. Design
of
PLL
(Cadence
Virtuoso):
• Designed
a
working
Phased
Locked
Loop
using
a
bang
bang
phase
detector,
charge
pump,
Low
pass
filter
and
5 stage
ring
oscillator
which
works
with
the
central
frequency
of
500MHz. Design
of
2- Stage
Op- Amp
[Virtuoso
Schematic
&
Layout
Editor]:
• Designed
a
2- stage
Op- Amp
in
Virtuoso
Schematic
Editor
and
performed
AC,
DC,
Transient
and
Noise
Analysis.
• Created
Layout
using
Virtuoso
Layout
Editor
and
then
extracted
and
LVS
verified.
• Achieved
a
gain
margin
of
60dB,
phase
margin
of
53
degrees
with
a
power
limit
5mW.
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