RAHUL RATHORE Specialization: M.Tech. VLSI Design

th

Address: **, * *****, ******** ******, Contact No: +91-973*-***-***

BabusabPalya, Bangalore – 560043. E-mail id: acf9dp@r.postjobfree.com

1. OBJECTIVE

To build a career in VLSI industry, that broadens my existing skills and completely devoted with sincere efforts towards

the growth of organization.

2. PROFESSIONAL EXPERIENCE

1. Smart Chip Design Pvt. Ltd. (ASIC Verification Training Institute) (July 2014 – Till Present)

• Position : ASIC Verification Engineer Trainee.

2. National Aerospace Laboratories, Bangalore (May 2012 – July 2012)

• Position : Project Engineer.

3. National Aerospace Laboratories, Bangalore (April 2011 – April 2012)

• Position : Project Graduate Trainee.

3. TECHNICAL SKILL SUMMARY

Good knowledge in Physical Design Flow.

Good knowledge in Static Timing Analysis.

Perform Physical Design Steps for different designs for 2 semesters in M.Tech.

Good knowledge in Building verification Environment in SystemVerilog and UVM.

Experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog.

Experience in using industry standard EDA tools for the front-end design & verification and Physical

Design.

Experience with Altera development tools.

4. TOOLS & LANGUAGE SKILLS

Subjects Digital Circuits, STA, Physical Design, ASIC, Verification.

Programming Languages Verilog HDL, VHDL, System Verilog, C/C++, MATLAB.

Front-end EDA Tools QuestaSim, ModelSim,

Quartus II, Cadence NC Launch.

Back-end EDA Tools Cadence Virtuoso, RTL Compiler & SoC Encounter.

Other Tools Keil.

Scripting Languages Perl & TCL.

Hardware FPGA (Altera DE2 Board), Microcontroller (8051, PIC 16XX and ARM7).

Operating Systems Linux, Windows 8.

Protocols AMBA AHB

Methodologies UVM.

5. EDUCATIONAL QUALIFICATIONS

Course/Degree Month & Year Percentage/CGPA Institute

M.Tech. (VLSI Design) June 2014 7.64 CGPA VIT University, Vellore

Institute of Engineering & Technology,

B.Tech. (Electronics &

June 2010 68.7% Bundelkhand University, Jhansi

Communication)

H.S.C March 2005 69.0% St. Mary’s Inter College

S.S.C March 2003 66.67% St. Mary’s Inter College

6. PROJECT DETAILS

SMART CHIP DESIGN PVT. LTD.

1. Verification of Network-on-Chip Routing Switch.

A routing switch is a networking device that operates at the Data Link layer of the OSI model. These switches filter and

forward the incoming packets to a destination port based on the address contained in the packet.

• Design of NOC Routing Switch.

• Simulation is performed using Questasim.

• Verification is performed using System Verilog and UVM.

• Use Constrained Random Method.

M.TECH. PROJECTS

1. Carry select adder using FINFET technology - May’14.

As CMOS technology continues to scale downward, CMOS structures prove inadequate for maintaining acceptable

device characteristics due to the short channel effects. FINFET technology proves a significant reduction of short-

channel effects. Addition is a most important arithmetic operation used in ALU of a computing device and its

performance will improves the performance of the whole system.

• Design FINFET transistor cell.

• Implement Carry Select Adder.

• Simulation is performed using Cadence-Virtuoso, Hspice.

2. AMBA-APB for UART Applications - Feb’14.

The design of the AMBA-Advanced Peripheral Bus (APB) controller provides an effective way to communicate between

the high performance peripherals and the low bandwidth peripherals. APB Bridge is designed for conversion and

decoding of AHB signals to APB signals.

• Design modules for AHB-APB Bridge and UART.

• Simulation is performed using Modelsim and Cadence-NC Launch.

• Synthesis is performed using Quartus II, Cadence-RTL Compiler.

• Physical design steps are performed using Cadence SoC Encounter.

3. Verification of SRAM - Aug’13.

Along with the design of a complex digital circuit, its verification is also important. The verification of SRAM is

performed using the concept of Bus Functional Model (BFM) and random test generation.

• Design module for SRAM.

• Implement BFM at Transaction Level.

• Write a TCL script to perform synthesis these modules.

• Physical design steps are performed using Cadence SoC Encounter.

• Tools used: Modelsim, RTL Compiler & SoC Encounter.

4. CORDIC design for fixed angle of rotation - May’13.

CORDIC algorithm performs several computing tasks such as the calculation of trigonometric, hyperbolic, exponential

and logarithmic functions, solution of linear systems, and many others. CORDIC algorithms are useful in signal and

image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical

computation.

• Design CORDIC modules with different architectures.

• Simulation is performed using Modelsim and Cadence-NC Launch.

• Synthesis is performed using Quartus II, Cadence-RTL Compiler.

• Physical design steps are performed using Cadence SoC Encounter.

5. PCI bus arbiter - Nov’12.

PCI bus arbiter architecture allows bus mastering of multiple devices on the bus simultaneously, which

allows a bus master to transfer data at the maximum permissible rate.

• Design module for PCI Bus Arbiter.

• Tools used: Modelsim and Cadence-NC Launch.

6. Floating-Point Multiplier - Sep’12.

In real world, the floating point arithmetic operations are performed for determining the accuracy in calculation. But in

the field of digital electronics, it is not directly possible to compute floating point numbers. Hence the floating point

multiplier logic is designed to perform operations on floating point numbers in binary terms.

• Design module for floating-point multiplier.

• Tools used: Modelsim.

NAL PROJECTS

1. Characterization of EM Wave Propagation in multi-layered metamaterial-dielectric media - Jul’12.

Metamaterials have more absorbing property for electromagnetic waves than the dielectric materials. The behavior of

permittivity and permeability of metamaterials and even the ray-tracing inside the multi-layered metamaterials is entirely

different from the dielectrics.

• Objective is to reduce Radar Cross Section of an aircraft.

• Develop a code for metamaterial-dielectric media.

• Tools used: C and Matlab.

2. Characterization of EM Wave Propagation in multi-layered Dielectric media - Mar’12.

In aerospace applications, the multi-layered dielectric materials are used to cover the metal body of the aircrafts.

Working with the conventional methods to find the Transmission and Reflectance by studying the behavior of

permittivity and permeability on the losses of different materials and carrying out the ray tracing inside multi-layered

dielectrics on the body of aircrafts.

• Objective is to reduce Reflectivity of em wave from aircraft.

• Develop a code for dielectric media.

• Tools used: C and Matlab.

3. Mutual Coupling in Adaptive Antenna Arrays - Nov’11.

In aerospace defense applications, the adaptive antennas are used to place nulls in an undesired direction and

maintains the sufficient gain in the desired direction. The mutual coupling effect in antenna arrays degrades the

performance of an adaptive antenna in terms of gain and bandwidth.

• Objective is to improve the performance of an adaptive antenna.

• Develop a code for Adaptive Antenna Arrays.

• Include the mutual coupling effect

• Compare the simulation for different configuration.

• Tools used: C and Matlab.

RESPONSIBILITIES

• Interacting with the scientists about the requirements for the day.

• Conduct a research on the existing research papers.

• Defining the problem with formula, write the algorithm and code.

• Compare the experimental values with standard values for accuracy considerations.

• Validate and plot the graphs.

• A project document was written to show how this issue could be resolved.

B.TECH. PROJECT

1. Sub-Optimal Controller using Model Reduction Technique - May’10.

• Develop a code for Sub-optimal controller in C.

7. ACHIEVEMENTS

Paper published on “Design of High Speed, Low Power Error Tolerant Adder” in International Journal of

Applied Engineering Research (IJAER), ISSN 0973-4562 Vol. 9, number 14 (2014) pp. 2711-2720.

Paper published on ‘The Effect of Mutual Coupling in Active Radar Cross Section (RCS) Reduction’ in

2012 IEEE International Symposium on Antennas and Propagation, Chicago, USA, paper# 1060.

Qualified the GATE exams in 2011 and 2012.

8. DECLARATION

I hereby declare that, to the best of my knowledge, the above information is true.

Place: Bangalore

Date: 27/09/14 (RAHUL RATHORE)

Contact this candidate