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Engineer Project

Location:
Bengaluru, KA, India
Posted:
September 29, 2014

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Resume:

RESUME

ABHISHEK.B.C.

: ******.****@*****.*** Mobile: 990*******

Career Objective

To seek a challenging and career oriented job, which enables me to update with the emerging

latest Technology and provides scope for widening the spectrum of my knowledge.

Professional Experience

Designation : ASIC IP Design and Verification Project Trainee/Intern.

Company : LSI India Research and Development Private Limited

Experience : 1 Year

Designation : Engineer.

Company : Mindtree Ltd.

Experience : 1 Year 2 Months.

Technical Skills

CMOS VLSI Design, Digital Electronics.

Operating System :LINUX,MAC.

Languages : C language,Microprocessor-8086 ALP, Basics of Objective C.

Scripting Language : PERL,Makefile[Beginner].

HDL : VHDL, Verilog, SystemVerilog

Verification Methodology : UVM.

Synthesis Tool : Design Compiler (Synopsys)(Beginner), VCS(Synopsys)

STA : Prime Time (Synopsys) (Beginner).

Schematic /Layout Editor :Virtuoso (Cadence)(Beginner), Microwind,DSCH

Load Balancing Tool : LSF (Load Sharing Facility)

Qualification tool : Certitude.

Application/Tool : MATLAB,Xcode,Clang, Instruments,SVNX, Ellysis.

Trainings Undergone

Embedded Learning program under Embedded Technology Practice in

PES(ProductEngineering Services) at Mindtree Ltd.

“FEEL EMPLOYABLE” Conducted by CLHRD at BIET Davangere.

SOFTSKILL Foundation Program under the aegis of the Infosys Campus

Connectprogram at BIET Davangere.

One day workshop at Maven-Silicon on ASIC Design and Verification.

Projects.

Ethernet Subsystem verification at LSI.

Worked with a team of highly motivated verification engineers to verify the Ethernet

subsystem using System Verilog, UVM. Involved in creating testcase and debugging.

Designed modules like Serial In Parallel Out and Parallel In Serial Out to interface VIP.

Auto-Negotiation (AN) IP Verification using System Verilog and UVM at LSI.

The AN IP allows an Ethernet device to advertise modes of operation it possesses to another

device at the remote end of a Backplane Ethernet link and to detect corresponding operational

modes the other device may be advertising. Verified this IP using UVM and System Verilog.

Jabra Mac Suite (JMS) at Mindtree:

Worked with a dedicated team of MAC engineers to implement the JMS using Objective C

and MAC tools. Involved in unit testing of the modules and analysis of the packets

transferring from the softphone to the head set and vice versa.

Secure File Transfer Protocol (FTP) at Mindtree:

Secure File Transfer Protocol is a protocol where the whole file is encrypted at the user

terminal and stored at the server terminal where the files are stored under user name folder.

The user has to provide the user name and file name. The user will receive the encrypted file

and the user needs to enter the password to decrypt the file. Implemented SFTP using C.

Projects/Seminars during Post graduation, M.Tech.

4thSemester:

Verification of AHB-LITE using UVM.

rd

3 Semester:

Verification of simple switch/router using System Verilog, UVM, Synopsys (VCS).

Implemented FIFO using Synopsys VCS.

2st Semester:

Implemented PLL and SRAM using Cadence (virtuoso).

1stSemester:

Implemented all basic gates and simple circuits using Cadence virtuoso.

Implemented IEEE paper Low Power and Area Efficient Carry Select Adder using

DSCH and Microwind.

Seminar on Tri-Gate Transistor Technology.

Project during graduation, B.E.

Robotic Vision Using MATLAB.

The objective of our project is identification and tracking of the object: Red colored ball. The

Robot captures the image of an object with the help of the web cam. The captured frame is

processed using MATLAB. According to the position of the object the control signal is

transmitted. The robotic movement is according to the control signal relayed.

Education

Year of Name of the

passing Course Institute Board/University Percentage

2014 M.Tech(VLSI Design SJCE,Mysore Visvesvaraya Technological 71.95

and Embedded University, Belgaum

Systems)

2011 B.E.,E&C B.I.E.T. Visvesvaraya Technological 78.65

Davangere University, Belgaum

2007 P.U.C. Bapuji Science PU Pre-University Board, 89.2

college Karnataka (PCM=94.67)

2005 S.S.L.C M.E.S Convent Karnataka Secondary 84.8

Education Board, Karnataka

STRENGTHS: Hard working and Honest, Positive thinking, Proactive.

HOBBIES: Solving SU-DOKU, Playing Shuttle and cricket, Watching Movies.

I hereby declare that above information provided is correct to the best of my knowledge. I

shall work to the best of my abilities which will add more values to your organization.

Date: August 2014 (ABHISHEK.B.C.)



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