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MANOJ G

: acf6hr@r.postjobfree.com : +91-966*******

CAREER OBJECTIVE

To seek assignments which would enrich knowledge, deliver value added expertise where there is scope for learning new skills and challenging work environment in Semiconductor sector.

WORK EXPERIENCE

* A budding professional with over >2 years of experience in ASIC Verification, Full Chip Validation, PLCs

* Worked 13 months at Intel Corporation, Bangalore, India (August 2013–August 2014)

Responsible for Full Chip Verification of Intel Xeon Server using System Verilog & OVM

* Worked as Associate Engineer at MARS TECHNOLOGIES, Bangalore (July 2012–October 2012)

* Worked as Trainee Engineer at BOSCH (RBIN), Bangalore (January 2012 – May 2012)

TECHNICAL SKILLS

Skills : C, Perl, Ruby, System Verilog, Assembly, HVL, Physical design and Validation

Software Tools : Kiel, Matlab, Xilinx, Modelsim, Cadence Encounter, Cadence virtuoso, Synopsys VCS

Platforms : UNIX and Windows

Protocols : AMBA, AHB, AXI

Interests : DFT, SoC, STA, CTS, RTOS, Testability, Verification methodology

AREAS OF STRENGTH

* Good communication skills, deterministic, self-motivated and adaptable team player

* Understanding of processor architecture and awareness of RTL to GDS flow

* Front end design flow, design automation, constrained random validation and DFT

* Microcontrollers, Digital logic, Assembly language,STA and Chip level simulations

* ASIC Verification using System Verilog, System Verilog Assertions, UVM and Functional Coverage

ACADEMIC PROFILE

* M.Tech in VLSI Design and Embedded Systems, RVCE, Bangalore with an aggregate of 75%

* B.E in Electronics and Communication, Visweswaraya Technological University, APSCE, Bangalore with an aggregate of 70%

PROJECTS

M.Tech Final Year Project at Intel Corporation – Aug 2013 - Aug 2014

Title: HVM content development for next generation Intel Xeon based processor in pre-silicon Environment

Position: Post Graduate Technical Intern

* As an Intern was responsible for Full Chip functional test content development and verification of architectural design of Intel Xeon sever using HVM flow.

* The test vectors developed using DFT features for the coverage perspective targeting the functional units.

* The chip is verified using System Verilog coding (OVM) and simulations are performed for multi-core processors in pre-silicon environment which are debugged for failures, documented & path cleared.

Industrial Project at BOSCH (RBIN) Limited – Jan 2012 - May 2012

Title: Up gradation of PLC of Parishud Machine for automatic processing

* The prime concern is to add upon and refine the existing features of the machine using a controller to reduce the number of man power and manufacturing time.

* Programming the Siemens and Bosch (Rexroth) controller for the particular functionality in different environment to obtain the precision finish of a tool.

Title: Novel 6T SRAM Design

* Divided bit lines into dynamic cell stability while reducing the power consumption comprehensively by decreasing the active energy.

* Utilizing dynamic decoder which overcomes the static power consumption and improves the cell’s read stability thereby increases memory speed at a very low energy cost.

Title: Low Voltage Differential Signal driver compliance with IEEE 1596.3 - LVDS standards

* LVDS driver is implemented using NMOS switches with top and bottom bias MOSs (as voltage sources)

* Biases were generated using two stage differential amplifier circuit by reaching IEEE specification in 90nm technology; e.g. Diff voltage 300mV, speed 800MHz, Common Mode voltage 1.2V

Title: A New VLSI Architecture of Parallel Multiplier–Accumulator (MAC DESIGN) based on Radix-2 Booth and Wallace tree multiplier algorithm

* Implemented a encoder and decoder circuit for the MAC at a low power and high speed along with simultaneous operations by encountering appropriate Setup and Hold time for the design.

Title: Crosstalk immune VLSI scheduling based on genetic algorithm using High Level Synthesis

* Using genetic analysis, retaining the positive edges upgraded the design to be capable of sustaining crosstalk by speed up for computation in successive generation.

BE Final Year Project – September 2011 – February 2012

Title: GPS, GSM & RFID based Biometric implementation for a Public Transport System

* To ensure the utilization of recent technology by automating the transport system right from ticket issue till the safe travel by enabling, tracking and sending the acknowledgement using RFID, GPS and GSM

* The key chain process was in synchronization to permit after authentication, calculate the distance and send a note to the passenger with a unified approach and was effectively worked out

ACCOMPLISHMENTS

* Qualified GATE-2012 in the first attempt

* Recognized for optimization of operation flow from technical team (Siemen’s and Rexroth) at BOSCH

* Participated in 26th IEEE International Conference on VLSI and Embedded System during Feb 2013

* Attended UVM training from Cadence held in Bangalore during 2013

* Participated in state level quiz and bagged the awards

PERSONAL DETAILS

Date of Birth: 27 June 1990

Address: #1602, 15th cross, 6th main, 'D' Group Layout, Srigandadakaval, Vishwaneedam Post, Bangalore-560091

Linguistics: English, Hindi, Kannada, Telugu and Tamil

Passport no: K3829134

DECLARATION

I hereby declare that all the above information is true to the best of my knowledge.

PLACE: Bangalore [MANOJ.G]

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