C u r r iculum Vitae

HARSHA N,

Mobile : +91-953*******

Email Id : acg5ss@r.postjobfree.com

Career Objective:

Seeking a challenging and responsible position as an Digital Design and Verification Engineer in the

organization, that makes full use of my existing skills, as well as gives me an opportunity to develop new ones .

P rofessional Summa ry:

A dynamic and competent professional with 1+ year of experience in VLSI industry as a Design &

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Verification Engineer.

Good understanding of the ASIC and FPGA design flow.

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Experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog and UVM.

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Experience in using industry standard EDA tools for the front end design and verification.

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Good knowledge in FPGA based hardware design.

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Good knowledge in Static Timing Analysis (STA).

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Good knowledge in architecture of Spartan6 (LX75 & LX45),Spartan3 and CPLD devices.

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Good knowledge in Orcad Capture CIS tool.

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Good knowledge in ARM based microcontrollers.

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Fair enough knowledge on Perl Scripting.

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Fair enough experience in using Assertion based verification(ABV) and Coverage Driven Verification(CDV).

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Good exposure in Digital and Analog Electronics circuits understanding and analyzing.

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Result oriented and interested to learn new technologies.

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Technical Skills:

HDL Verilog

HVL System Verilog

Verification Methodologies Code Driven Verification and Assertion Based Verification

Testbench Methodologies UVM (Universal Verification Methodology)

Tools Used Model Sim, Xilinx ISE Design suite, Questa Sim, PlanAhead, Orcad Capture CIS

Scripting Language Perl

RTL Coding & Synthesis, FSM Based Design, CMOS fundamentals, Simulation,

Code Coverage, Functional Coverage, STA Concept, Perl Scripting, Motor Driver

Knowledge IC’s, H-Bridges, MOSFET drivers, Regulators, Analog circuits, Digital Circuits,

Hardware Designing, Arm based microcontrollers(LPC ),BOM preparation, net

list verification .

Protocols SPI,I2C,UART,AMBA

C ertification Course:

“Advance VLSI Design and Verification Course” done at Maven Silicon Softtech Pvt.Ltd in Bangalore

during the period of Jan – 2013 to May – 2013.

M ini P rojects:

HDL & HVL : Verilog, System Verilog/UVM.

EDA Tools : Modelsim, Questa Sim – Verification Platform and ISE Design Suit.

R outer1x3 – RTL design and Verification using UVM.

Architected the design and described the functionality using Verilog HDL.

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Preparation of verification plan.

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Identification of Test cases.

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Verification Plan review and modification.

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Preparation of Test cases.

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Test Bench coding.

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Verified the RTL model using UVM.

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Generated functional and code coverage for the RTL verification sign off.

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Real Time Clock – RTL design and verification

Implemented the Real Time Clock using Verilog HDL independently.

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Architected the class based verification environment using system Verilog.

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Verified the RTL model using system Verilog.

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Generated functional and code coverage for the RTL verification sign off.

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Synthesized the design.

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Dual Port RAM – verification

Implemented the Dual Port Ram using Verilog HDL independently.

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Architected the class verification environment using system Verilog.

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Verified the RTL module using System Verilog.

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Generated functional and code coverage for the RTL verification sign off.

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Design and Verification of UART IP Core

Architected the design and described the functionality using Verilog HDL.

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Preparation of verification plan.

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Identification of Test cases.

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Verification Plan review and modification.

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Preparation of Test cases.

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Test Bench coding.

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Verified the RTL model using UVM.

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Generated functional and code coverage for the RTL verification sign off.

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Design and Verification of SPI

Architected the design and described the functionality using Verilog HDL.

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Preparation of verification plan.

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Identification of Test cases.

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Verification Plan review and modification.

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Preparation of Test cases.

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Test Bench coding.

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Verified the RTL model using UVM.

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Generated functional and code coverage for the RTL verification sign off.

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P rofessional Experience:

• Maven Silicon Soft Tech Pvt. Ltd,

Duration : January 2013 – May 2013

Designation : Trainee

Duration : July 2013 – December 2013

Designation : Intern

• Panacea Medical Technologies Pvt. Ltd,- Bangalore,

Duration : December 2013 – till date

Designation : Graduate Engineer Trainee

P rojects Handled:

MLC (Multi leaf collimator – Radiotherapy Device)

Project #1

Duration 6 month Location India (Bangalore)

Project Description: A multi leaf collimator (MLC) is a device made up of individual leaves of a high atomic

numbered material, usually tungsten, which can move independently in and out of the path of a particle beam in order to

block it. MLCs are used on linear accelerators to provide conformal shaping of radiotherapy treatment beams.

Specifically, conformal radiotherapy and Intensity Modulated Radiation Therapy (IMRT) can be delivered using MLC’s.

The shaping of radiations are controlled through the high precision, optical encoder feedback motors, where the motor

driver IC’s signals are controlled from the high end spartan6 series FPGA’s by implementing cordic core.

Responsibilities:

Architected the design of cordic algorithm for various rotation control and described the functionality using

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Verilog HDL.

Verification Plan review and modification.

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Preparation of Test cases.

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Test Bench coding.

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IO’s planning through PlanAhead tool for (LVDS and single ended CMOS i/o’s).

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Analysis of FPGA’s power consumption through ISE’s XPOWER ANALYZER tool.

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Hardware designing of FPGA, for interfacing with ARM based microcontroller and various other components.

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Digital mammography

Project #2

Duration 4 month Location Bangalore

Project Description: Digital mammography is a specialized device that uses digital receptors to examine the

breast tissue for breast cancer. The electrical signals can be read on computer screens, permitting more manipulation

of images to theoretically allow radiologists to more clearly view the results. Here the position of the device is controlled

from FPGA and CPLD’s by reading the value from the linear feedback potentiometers interfaced to ADC’s through SPI

communication.

Responsibilities:

Architected the design for SPI communication and described the functionality using Verilog HDL.

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Verification Plan review and modification.

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Preparation of Test cases.

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Test Bench coding.

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IO’s planning through PlanAhead tool for (LVDS and single ended CMOS i/o’s).

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Analysis of FPGA’s power consumption through ISE’s XPOWER ANALYZER tool.

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Choosing suitable voltage regulators for FPGA’s and driver IC’s for control profiles.

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Educational Qualifications:

Course Offered School/College Board Result Year

East Point College of Engineering

A nd Technology, Bangalore.

B.E (ECE) VTU Board 61.25% 2012

Govt. Boy’s Pre-university College,

I I PUC Karnataka PU Board 72.12% 2008

Kolar.

Karnataka SSLC

SSLC 83.24% 2006

Board

St’Annes High School, kolar.

Personal Details:

Name : Harsha N

Gender : Male

Date of Birth : 09th November 1990

Nationality : Indian

Hobbies : p laying cricket, volleyball, football, PC games and t ravelling.

Languages known : Kannada, H indi, English, Telugu.

Address : Padmini Nilaya, Karanjikatte 11th cross,

Kolar, Karnataka-563101

I hereby declare that the information mentioned herein is true to the best of my knowledge.

Place: Bangalore

Date:

HARSHA N

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