CURRICULUM VITAE

Leya .V.Thomas

Email:acf8x6@r.postjobfree.com

Mobile:+91-819*******

Bangalore

Entry level positions as Design/Verification Engineer preferably in ASIC

domain.

OVERVIEW

Good understanding in Digital logic design& Electronics fundamentals

Good understanding of the ASIC/FPGA design flow

Experience in Verilog HDL to write synthesizable RTL, self-checking test

benches&

Test benches in System Verilog

Very good knowledge on Verification methodologies(UVM)

Experience in using industry standard EDA tools for the Front-end Design and

Verification

Knowledgeable in STA concepts and timing calculations .

Synchronization of clock domains using: Handshaking signals, FIFO .

PROFESSIONAL QUALIFICATIONS

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore

Year : June 2014-November 2014

ACADEMIC QUALIFICATIONS

Bachelor of Technology in Electronics and Communication

Karunya University, Coimbatore

Aggregate : 77%

Higher Secondary Education

St marys Residential School,Thiruvalla,Kerala

Board:CBSE

Percentage : 66.4%

Secondary Education

Vimala Public School,Thodupuzha,Kerala

Board:CBSE

Percentage : 78.8%

TOOLS & TECHNICAL SKILLS

HDLs : Verilog

HVL : System Verilog

Verification

Methodologies : Coverage Driven Verification, Assertion Based

Verification

TB Methodology: UVM

EDA Tools : Modelsim and Xilinx-ISE

Domain : ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge : RTL Coding, FSM based design, Simulation, Code

Coverage,

Functional Coverage, Synthesis, Static Timing Analysis

Tool/Softwares : MATLAB,Pspice

Operating systems: Windows & Ubuntu

VLSI PROJECTS

Router 1x3 - RTL design and verification

HDL : Verilog

HVL : SystemVerilog

TB Methodology : UVM

EDA Tools :Modelsim, Questa-Verification Platform and Xilinx-ISE

Description :

> Architected the design and described and verified the functionality

using Verilog HDL.

> Generated Code coverage for the RTL verification sign-off Synthesized

the design

> Architecting the class based verification environment using UVM

> Verification of the RTL module using UVM

> Generation of functional coverage for the RTL verification

DECLARATION

I hereby declare that the information furnished above is true to the best

of my knowledge.

Leya.V.Thomas

Place: Bangalore

Reference on Request.

Contact this candidate