| Resume alert | Resumes 21 - 30 of 412 |
embedded engineer with pcb design engineer and vhdl basic coding
Bangalore, Karnataka, India
... Working on Carrier Card and FPGA using libero. Standalone testing of cards which includes visual inspection, impedance test, power on test and debugging the issues. BOM and schematics update using ORCAD. Have knowledge on working of OSAMC and ... - 2021 Feb 17
... Working on Carrier Card and FPGA using libero. Standalone testing of cards which includes visual inspection, impedance test, power on test and debugging the issues. BOM and schematics update using ORCAD. Have knowledge on working of OSAMC and ... - 2021 Feb 17
Electrical Design
Vasant Nagar, Karnataka, India
... ● Participated in Hands-on program "FPGA Design using Vivado" at CoreEL Technologies. ● Participated in Hands-on program using "Raspberry Pi". ● I have participated in NGO to paint a 100 year’s old school near Kolar. PERSONAL DETAILS: Name : Pramod ... - 2021 Feb 15
... ● Participated in Hands-on program "FPGA Design using Vivado" at CoreEL Technologies. ● Participated in Hands-on program using "Raspberry Pi". ● I have participated in NGO to paint a 100 year’s old school near Kolar. PERSONAL DETAILS: Name : Pramod ... - 2021 Feb 15
c, c++, verilog, vhdl, Cadence
Vasant Nagar, Karnataka, India
... Arm cortex m3, Basys 3 Artix- 7 FPGA, Raspberry pi3, Arduino Uno PROJECTS Bus tracking and alerting system for visually challenged personnel using RF RF signals transmitted by the bus were received and the respective audio output was generated. ... - 2021 Feb 15
... Arm cortex m3, Basys 3 Artix- 7 FPGA, Raspberry pi3, Arduino Uno PROJECTS Bus tracking and alerting system for visually challenged personnel using RF RF signals transmitted by the bus were received and the respective audio output was generated. ... - 2021 Feb 15
Data Design
Vasant Nagar, Karnataka, India
... Domain: Digital Design,ASIC/FPGA design flow, Methodologies. Knowledge on: RTL Coding, FSM based Design, simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis. Resume of Tejas Page 1 of 4 Summary Of Qualifications Good ... - 2021 Feb 13
... Domain: Digital Design,ASIC/FPGA design flow, Methodologies. Knowledge on: RTL Coding, FSM based Design, simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis. Resume of Tejas Page 1 of 4 Summary Of Qualifications Good ... - 2021 Feb 13
Engineer Engineering
Vasant Nagar, Karnataka, India
... • Hardware expertise: Altera FPGA board, Feko+ winprop 2018 software. Workshops attended/Papers presented • Have attended a MSP430 (2 day work shop) on how to visualize and design a micro-controller and also studying the performances regarding the ... - 2021 Feb 13
... • Hardware expertise: Altera FPGA board, Feko+ winprop 2018 software. Workshops attended/Papers presented • Have attended a MSP430 (2 day work shop) on how to visualize and design a micro-controller and also studying the performances regarding the ... - 2021 Feb 13
Design Engineering
Vasant Nagar, Karnataka, India
... verification TB Methodology: UVM EDA Tools: Questa-Sim – Mentor Graphics Riviera Pro – Aldec ISE - Xilinx Domain: ASIC/FPGA front-end Design and Verification Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage ... - 2021 Feb 12
... verification TB Methodology: UVM EDA Tools: Questa-Sim – Mentor Graphics Riviera Pro – Aldec ISE - Xilinx Domain: ASIC/FPGA front-end Design and Verification Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage ... - 2021 Feb 12
Design Power
Vasant Nagar, Karnataka, India
Boards: FPGA (Spartan *E & Spartan *), ARM Cortex-M3, Arduino (UNO, Mega, Leonardo & Nano). Operating Systems: Windows, Unix, Linux. ACADEMIC PROJECTS PROJECT 1 2018-2019 + Title: Design, Verification of Memory IP Core using System Verilog * HDL: ... - 2021 Feb 12
Boards: FPGA (Spartan *E & Spartan *), ARM Cortex-M3, Arduino (UNO, Mega, Leonardo & Nano). Operating Systems: Windows, Unix, Linux. ACADEMIC PROJECTS PROJECT 1 2018-2019 + Title: Design, Verification of Memory IP Core using System Verilog * HDL: ... - 2021 Feb 12
Engineering Personal
Bangalore, Karnataka, India
... TECHNICAL QUALIFICATION: Area of interest: VLSI Design, FPGA, Embedded Systems, PCB Design Programming and Scripting: Basics of C Programming, Basics of Verilog Simulation tools: Keil, Linux Operating Systems: Red hat, Windows XP/7/8/8.1/10 ACADEMIC ... - 2021 Feb 08
... TECHNICAL QUALIFICATION: Area of interest: VLSI Design, FPGA, Embedded Systems, PCB Design Programming and Scripting: Basics of C Programming, Basics of Verilog Simulation tools: Keil, Linux Operating Systems: Red hat, Windows XP/7/8/8.1/10 ACADEMIC ... - 2021 Feb 08
Machine Engineer
Bangalore, Karnataka, India
... Design and Implementation of an Efficient Embedded Cryptography Algorithm using FPGA. (Bachelor of Engineering) Review: This project proposes a new embedded encryption algorithm based on linear feedback shift register. Because the algorithm is only ... - 2021 Feb 08
... Design and Implementation of an Efficient Embedded Cryptography Algorithm using FPGA. (Bachelor of Engineering) Review: This project proposes a new embedded encryption algorithm based on linear feedback shift register. Because the algorithm is only ... - 2021 Feb 08
Project Personal
Bangalore, Karnataka, India
... Requirements: Spartan 6 FPGA, BLDC/BDC motor, JTAG emulator, etc.., • Mini project: IoT based scrolling display. Aim: The aim of this project is to display the notifications in the display board from anywhere using IP Protocol. Requirements: Arduino ... - 2021 Feb 02
... Requirements: Spartan 6 FPGA, BLDC/BDC motor, JTAG emulator, etc.., • Mini project: IoT based scrolling display. Aim: The aim of this project is to display the notifications in the display board from anywhere using IP Protocol. Requirements: Arduino ... - 2021 Feb 02