M VinodKumar

**/**, ********* **** ******:+91-944*******

Yemmiganur Email: adabjz@r.postjobfree.com

Kurnool

AP, India-518360

Carrer Objective

Looking for a challenging role in a reputable organization to utilize my technical database, and management skills for the growth of the organization as well as to enhance my knowledge about new and emerging trends.

Hands on Experience

Advanced VLSI Design and Verification course

Maven Silicon VLSI Design and Training Center,Bangalore

April 2019 to till date

Educational Qualification

S.NO

Name of Examination

School/College

University / Board

Year

Percentage

1

B.Tech.

(Electrical & Electronics Engineering

JNTU College of Engineering

Pulivendula.

Jawaharlal Nehru Technological

University,

Anantapur

2018

73.84%

2

Intermediate

(M.P.C)

Narayana Jr.College, Yemmiganur

Board of Intermediate

2014

96.4%

3

SSC

Sri Venu Vidyalayam

High School,

Yemmiganur

Board of Secondary Education

2012

92%

VLSI Domain Skills

HDL : Verilog

HVL : System Verilog

Verification Methodology : Coverage Driven Verification, Assertion Based Verification

TB Methodology : UVM

Protocols : AXI, AHB, UART, I2C, SPI

EDA Tools : QuestaSim – Mentor Graphics, Riviera Pro – Aldec, ISE – Xilinx

Domain : ASIC/FPGA front-end Design and Verification

Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage,

Functional Coverage, Static Timing Analysis, ABV- SVA

Technical Skills

Productivity Tools : M.S.Office, Hardware (computer components assembling)

Operating system : Windows 10,Windows 7,Linux OS

Internships

Internship in Bharath Heavy Electrical Limited (Hyderabad) based on manufacturing of synchronous machines.

Curriculum Project

Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Responsibilities:

Architected the block level structure for the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design.

Academic Project

Economic Load Dispatch Of Thermal Power plants Considering Generator Constraints

In this project we had solved the IEEE paper based on Particle Swarm Optimization (Concept of Birds Flocking & Fish Schooling)

The MATLAB programs were developed to solve Economic Load Dispatch Problem of an n-unit Plant through lambda iterative method and Particle Swarm Optimization.

Achievements

Selected as a Zonal level player in Basketball.

Selected as a Student Coordinator in UG.

Directing short films (RED-4).

Personality Traits

People’s Person

Workaholic

Collaborator

Area’s of Interest

Playing Basketball, Cricket

Short Film Directing

Declaration

I hereby declare that all above mentioned information is in accordance with fact or truth up to my knowledge and I bear the responsibilities for the correctness of the above-mentioned particulars,

Date:

Place: M VinodKumar

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