Developer Software

Ashwini N

#**, *** *****, *** *****,Shakti Ganapathinagar, Basaveshwaranagar, Bangalore-560079 888-***-**** ************@*****.*** Objective

Looking for a challenging career which demands the best of my professional ability in terms of technical and analytical skills, and help me in broadening and enhancing my current skills and knowledge. Education

BE 2018 DON BOSCO INSTITUTE OF TECHNOLOGY, KUMBALAGODU,BANGALORE

· Branch: Electronics and Communication

· Percentage :77.5 %

2ND

PUC 2014 VIVEKANANDA PU COLLEGE, BANGALORE

· Combination: PCMB

· Percentage: 85.66%

10TH 2012 VIVEKANANDA ENGLISH HIGH SCHOOL,BANGALORE

· Percentage: 87.84%

Skills & Abilities

TECHNICAL SKILLS

· Programming in C, Microcontrollers, Embedded Systems, C++, Linux, Operating Systems.

· Trained at SKILLFINITY on Embedded Systems, Automotive Domain, CGI Studio tool. WORKSHOPS ATTENDED

· Attended Workshop from 28/9/2015 – 29/9/2015 conducted on “NI Lab View “ in association with NI Lab View Academy, SJBIT Bangalore.

· Attended workshop on EMBEDDED SYSTEMS AND IOT conducted by ISM UNIV in 2017.

· Attended workshop on IMAGE PROCESSING by Don Bosco Institute Of Technology in 2015. WORK EXPERIENCE

· Currently Working as HMI developer for Car multimedia projects using CGI Scene composer as the tool at Robert Bosch through Spacegraph.

· CGI Studio tool mainly used for Hardware HMI and GUI interfaces in Infotainment Systems. ACHIEVEMENTS

· Won Prizes in drawing, singing and essay competitions.

· Won three consecutive-Silver Medal for “Award of Excellence” in Academic year 2015, 2016, 2017 respectively by DBIT, Bangalore.

Page 2

Academic Project-BE(ECE)

TITLE: VITERBI DECODER DESIGN FOR SOFTWARE DEFINED RADIO ON FPGA (VLSI DOMAIN) DESCRIPTION:

A) Software defined radio adapts various modulation schemes, encoding techniques by changing its configuration. SDR reduces the cost complexity and provides the flexible communication system. B) The Viterbi decoder architecture with improved traceback unit for a code rate of 1/2 and a constraint length of k=3. This decoder finds advantages in software defined radio applications due to its area efficiency and speed. The decoder is simulated in Xilinx 14.1 and implemented in a field programmable gate array (FPGA).

Certification

· Participated in the workshop on “EMBEDDED SYSTEMS AND IOT” conducted by ISM UNIV on 25th Feb 2017.

Personal Details

Father’s Name : Nanjappa

Date of Birth : 28-10-1996

Gender : Female

Nationality : Indian

Languages Known : English and Kannada

Hobbies : Listening to music,Craft work

Extra-Curricular Activities

· Drawing

· Playing Badminton

DECLARATION:

I hereby declare that the above written particulars are true to the best of knowledge and belief. STATION: BANGALORE

DATE :

SIGNATURE

(ASHWINI N )

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