| Resume alert | Resumes 61 - 70 of 419 |
Software Developer Assistant
Vasant Nagar, Karnataka, India
... 2)Project name: Snake game using FPGA board Software : Xilinx vivado using verilog HDL. Team Size : 3 members Role : Front end designer. Organization : GVIT Project Supervisor (s): Mr.Aravind Kumar (Assistant Professor Dept. of ECE) Area/Domain of ... - 2019 Aug 17
... 2)Project name: Snake game using FPGA board Software : Xilinx vivado using verilog HDL. Team Size : 3 members Role : Front end designer. Organization : GVIT Project Supervisor (s): Mr.Aravind Kumar (Assistant Professor Dept. of ECE) Area/Domain of ... - 2019 Aug 17
Design Power
Vasant Nagar, Karnataka, India
... PERL(beginner level), System Verilog(beginner level) EDA TOOLS Synopsys EDA tools: IC compiler Prime time Cadence EDA tool: Cadence virtuoso Mentor graphics: Modelsim(HDL simulation) FPGA Synthesis Tool: Quartus altera Xilinx Vivado Design Suite. ... - 2019 Aug 08
... PERL(beginner level), System Verilog(beginner level) EDA TOOLS Synopsys EDA tools: IC compiler Prime time Cadence EDA tool: Cadence virtuoso Mentor graphics: Modelsim(HDL simulation) FPGA Synthesis Tool: Quartus altera Xilinx Vivado Design Suite. ... - 2019 Aug 08
electrical, Auto CADD etc..
Peenya, Karnataka, India
... M.Tech Main Project: “Design and FPGA Implementation of Reversible PROM, Adder & Subtracter using Reversible Decoder” The aim of this work is to design & synthesize of reversible PROM, Half Adder/Subtracter & Full Adder/Subtracter using reversible ... - 2019 Aug 07
... M.Tech Main Project: “Design and FPGA Implementation of Reversible PROM, Adder & Subtracter using Reversible Decoder” The aim of this work is to design & synthesize of reversible PROM, Half Adder/Subtracter & Full Adder/Subtracter using reversible ... - 2019 Aug 07
Design Project
Koramangala, Karnataka, India
... Hardware Systems : NXP ARM Cortex M3 (for Embedded Applications), Basys3 FPGA Board (Processor Based System Design) Technical Skills : Physical Design, Analog & Mixed Signal Circuit Design, STA and PCB Design. Hands on Analysis of different types of ... - 2019 Aug 07
... Hardware Systems : NXP ARM Cortex M3 (for Embedded Applications), Basys3 FPGA Board (Processor Based System Design) Technical Skills : Physical Design, Analog & Mixed Signal Circuit Design, STA and PCB Design. Hands on Analysis of different types of ... - 2019 Aug 07
FAE
Vasant Nagar, Karnataka, India
... TECHNICAL EXPERTISE • Design, Development and Testing of hardware-based boards for Defense & Aerospace applications based on Micro controller, FPGA and CPLD’s. • Expertise in Hardware Testing (ATP), Functional Testing of boards (FTP), Integration ... - 2019 Jul 28
... TECHNICAL EXPERTISE • Design, Development and Testing of hardware-based boards for Defense & Aerospace applications based on Micro controller, FPGA and CPLD’s. • Expertise in Hardware Testing (ATP), Functional Testing of boards (FTP), Integration ... - 2019 Jul 28
Good knowledge in C/C++.
Bangalore, Karnataka, India
... Language : C Platform : Windows 7/XP/8/10 using 8051 microcontroller Description The scope of the project was to design, develop and implementation of an efficient hardware architecture for VGA monitor controllers based on FPGA technology. The ... - 2019 Jul 20
... Language : C Platform : Windows 7/XP/8/10 using 8051 microcontroller Description The scope of the project was to design, develop and implementation of an efficient hardware architecture for VGA monitor controllers based on FPGA technology. The ... - 2019 Jul 20
Design Engineering
Vasant Nagar, Karnataka, India
... Pincode-560083 Mobile: +91-954******* LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Jul 12
... Pincode-560083 Mobile: +91-954******* LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Jul 12
Verilog, System Verilog, UVM, SOC Verification, ASIC Verification
Vasant Nagar, Karnataka, India
... • FPGA generic and specific code (Xilinx & Altera) for memory, clock adaption and JTAG tap. • System configuration in a single definition file. • Example firmware’s using UART and Ethernet. • Test bench included, simulating target software and ... - 2019 Jul 08
... • FPGA generic and specific code (Xilinx & Altera) for memory, clock adaption and JTAG tap. • System configuration in a single definition file. • Example firmware’s using UART and Ethernet. • Test bench included, simulating target software and ... - 2019 Jul 08
Engineer Design
Karnataka, India
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
Engineering Design
Vasant Nagar, Karnataka, India
... SUMMARY OF QUALIFICATIONS: Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using ... - 2019 Apr 19
... SUMMARY OF QUALIFICATIONS: Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using ... - 2019 Apr 19