| Resume alert | Resumes 21 - 30 of 111 |
Engineer Engineering
Austin, TX
... 2019/05 – 2019/08 Library Characterization Intern ● Comparison of characterization tool between Synposys and Cadence. Skills ● Programming: C/C++, Perl, Python, SystemVerilog ● BEOL RC Deck Modeling and CMOS/FinFET Device Characterization ... - 2020 Feb 10
... 2019/05 – 2019/08 Library Characterization Intern ● Comparison of characterization tool between Synposys and Cadence. Skills ● Programming: C/C++, Perl, Python, SystemVerilog ● BEOL RC Deck Modeling and CMOS/FinFET Device Characterization ... - 2020 Feb 10
Design Engineer Software Developer
Austin, TX
... Highly skilled in ASIC/VLSI design and proficient in physical design flow and layout extractions, timing analysis, clocking of the circuits, DRC check, LVS check using design tool like Cadence, Mentor Graphics Calibre etc. EDUCATION: University at ... - 2019 Mar 07
... Highly skilled in ASIC/VLSI design and proficient in physical design flow and layout extractions, timing analysis, clocking of the circuits, DRC check, LVS check using design tool like Cadence, Mentor Graphics Calibre etc. EDUCATION: University at ... - 2019 Mar 07
Engineer Electrical
Austin, TX
... EXTRACURRICULAR Software SKM, AutoCAD, Matlab, PSPICE, ETAP, NC SIM, NC Verilog, Altium Designer, LabView, Cadence, QtSpim, Accubid, On-Screen Takeoff, Bluebeam, B2W, Aspen, SmartPlant, NavisWorks Programming Languages Basic understanding of Verilog ... - 2019 Jan 20
... EXTRACURRICULAR Software SKM, AutoCAD, Matlab, PSPICE, ETAP, NC SIM, NC Verilog, Altium Designer, LabView, Cadence, QtSpim, Accubid, On-Screen Takeoff, Bluebeam, B2W, Aspen, SmartPlant, NavisWorks Programming Languages Basic understanding of Verilog ... - 2019 Jan 20
Engineer Design
Austin, TX
... • Run the synthesis tools to implement the block from RTL to layout in form of OASIS (newer format of GDSII) using Cadence Space-based Router (equivalent to Synopsys ICC). • Analyze the timing of the circuit of a block or macro and redesign if ... - 2018 Jul 17
... • Run the synthesis tools to implement the block from RTL to layout in form of OASIS (newer format of GDSII) using Cadence Space-based Router (equivalent to Synopsys ICC). • Analyze the timing of the circuit of a block or macro and redesign if ... - 2018 Jul 17
Design Engineer
Austin, TX
... C++ (6 years) and scripting language Perl (2 years) TECHNICAL SKILLS Logic Synthesis Tools: Xilinx Vivado, Xilinx ISE, Cadence RTL Compiler Layout Tools: Cadence Virtuoso, Cadence Encounter Simulation Tools: Modelsim, Altera Quartus, SPICE, ... - 2018 Jun 16
... C++ (6 years) and scripting language Perl (2 years) TECHNICAL SKILLS Logic Synthesis Tools: Xilinx Vivado, Xilinx ISE, Cadence RTL Compiler Layout Tools: Cadence Virtuoso, Cadence Encounter Simulation Tools: Modelsim, Altera Quartus, SPICE, ... - 2018 Jun 16
Electrical Engineer Design
Austin, TX
... Expert with Cadence ADE toolset. Experience with factory and test personnel on IC problems. Extensive experience with LVS & DRC tools (Calibre & Cadence) Experienced with Cadence circuit layout and layout XL. Test chip creation (floor planning, DRC ... - 2018 May 31
... Expert with Cadence ADE toolset. Experience with factory and test personnel on IC problems. Extensive experience with LVS & DRC tools (Calibre & Cadence) Experienced with Cadence circuit layout and layout XL. Test chip creation (floor planning, DRC ... - 2018 May 31
Design Electrical Engineering
Austin, TX
... TECHNICAL SKILLS Programming Languages: C, C++, MATLAB, Python HDL/HVL: Verilog, VHDL, SystemVerilog, SystemC, UVM OS/Simulators: UNIX, GEM5, Xilinx ISE, Design Vision, Code Composer, HSPICE, PRIMETIME, ModelSim, OpenCV Design tools: Cadence Design, ... - 2018 May 22
... TECHNICAL SKILLS Programming Languages: C, C++, MATLAB, Python HDL/HVL: Verilog, VHDL, SystemVerilog, SystemC, UVM OS/Simulators: UNIX, GEM5, Xilinx ISE, Design Vision, Code Composer, HSPICE, PRIMETIME, ModelSim, OpenCV Design tools: Cadence Design, ... - 2018 May 22
Web Services Java
Austin, TX
... The markdown life cycle will be maintained via a markdown cadence in IMS that dictates when and at what threshold to take new markdowns. Physical inventory will be handled by creating a separate download file which contains reduced tag inventory. ... - 2018 May 16
... The markdown life cycle will be maintained via a markdown cadence in IMS that dictates when and at what threshold to take new markdowns. Physical inventory will be handled by creating a separate download file which contains reduced tag inventory. ... - 2018 May 16
Electrical Engineering
Hutto, TX, 78634
... touch screen panel using TI’s MSP430 MCU for integration with an augmented reality board game application TECHNOLOGY AWR, Cadence, Xilinx, Verilog, LabVIEW, C, C++, Java, Assembly, Matlab, Linux, SPICE, Solidworks CERTIFICATIONS “Introduction to ... - 2018 Mar 17
... touch screen panel using TI’s MSP430 MCU for integration with an augmented reality board game application TECHNOLOGY AWR, Cadence, Xilinx, Verilog, LabVIEW, C, C++, Java, Assembly, Matlab, Linux, SPICE, Solidworks CERTIFICATIONS “Introduction to ... - 2018 Mar 17
Electrical Engineer Engineering
Austin, TX
... EE bring-up and troubleshooting Statistical analysis Data collection Supply chain management Overseas manufacturing support Cadence OrCAD and basic Allegro ASIC level characterization and validation Construction of test plans Basic programming in C ... - 2018 Feb 13
... EE bring-up and troubleshooting Statistical analysis Data collection Supply chain management Overseas manufacturing support Cadence OrCAD and basic Allegro ASIC level characterization and validation Construction of test plans Basic programming in C ... - 2018 Feb 13